COA (Computer Organization and Architecture)
- COA Introduction
- Floating Point Number Representation in IEEE 754
- Booth’s Algorithm with Solved Example part 1
- Booth’s Algorithm with Solved Example part 2
- Booth’s Algorithm with Solved Example part 3
- Numerical Data Representation
- Restoring Division Part 01
- Restoring Division Part 02
- Non Restoring Division Part 01
- Non Restoring Division Part 02
- RISC Microprocessor
- CISC Microprocessor
Processor Organization and Architecture
Control Unit Design
- Memory and its characteristics
- DRAM ( Dynamic RAM )
- SRAM (Static RAM)
- Cache Memory Full Concept with working
- Memory Hierarchy and Locality of Reference
- Memory Interleaved
- Virtual Memory & Paging concept
- Memory Segmentation
- Demand Paging
- Cache Coherence Single & Multi Processor
- Cache Coherence Strategies
- MESI Write invalidate snoopy protocol
I/O Organization and Peripherals
Advanced Processor Principles
COA (Computer Organization and Architecture)
COA (Computer Organization and Architecture) is the semester 4 subject of computer engineering at Mumbai University.
The prerequisite of this subject is Digital Logic Design and Application. Course Objectives of the subject Computer Organization and Architecture is to have a thorough understanding of the basic structure and operation of a digital computer. To discuss in detail the operation of the arithmetic unit including the algorithms & implementation of fixed-point and floating-point addition, subtraction, multiplication & division. To study the different ways of communicating with I/O devices and standard I/O interfaces. To study the hierarchical memory system including cache memories and virtual memory. Course Outcomes of the subject Computer Organization and Architecture At the end of the course student should be able to. To describe the basic structure of the computer system. To demonstrate the arithmetic algorithms for solving ALU operations. To describe instruction-level parallelism and hazards in typical processor pipelines. To describe superscalar architectures, multi-core architecture, and their advantages to demonstrate the memory mapping techniques. To Identify various types of buses, interrupts, and I/O operations in a computer system.
In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems. Some definitions of architecture define it as describing the capabilities and programming model of a computer but not a particular implementation. In other definitions computer architecture involves instruction set architecture design, microarchitecture design, logic design, and implementation. Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement representation in efficient way, i.e., less number of additions/subtractions required. It operates on the fact that strings of 0’s in the multiplier require no addition but just shifting and a string of 1’s in the multiplier from bit weight 2^k to weight 2^m can be treated as 2^(k+1 ) to 2^m. As in all multiplication schemes, booth algorithm requires examination of the multiplier bits and shifting of the partial product. Prior to the shifting, the multiplicand may be added to the partial product, subtracted from the partial product, or left unchanged according to following rules: The multiplicand is subtracted from the partial product upon encountering the first least significant 1 in a string of 1’s in the multiplier. The multiplicand is added to the partial product upon encountering the first 0 (provided that there was a previous ‘1’) in a string of 0’s in the multiplier. The partial product does not change when the multiplier bit is identical to the previous multiplier bit.
Module Overview of Computer Architecture & Organization consists of the following subtopics Introduction, Basic organization of computer. Block level description of the functional units. Data Representation and Arithmetic Algorithms Integer Data computation: Addition, Subtraction. Multiplication: unsigned multiplication, Booth‟s algorithm. Division of integers: Restoring and non restoring division, Floating point representation. IEEE 754 floating point number representation. Floating point arithmetic: Addition, Subtraction, Multiplication, Division. Module Processor Organization and Architecture consists of the following subtopics Von Neumann model, Harvard Architecture, Register Organization, Instruction formats, addressing modes, instruction cycle. Instruction interpretation and sequencing. ALU and Shifters, Basic pipelined data path and control, Data dependences, data hazards, Branch hazards, delayed branches, branch prediction Performance measures CPI, speedup, efficiency, throughput and Amdahl‟s law. Module Control Unit Design consists of the following subtopics Hardwired control unit design methods: State table, delay element, sequence counter with examples like control unit for multiplication and division ,Microprogrammed control Unit: Microinstruction sequencing and execution. Micro operations, Wilkie‟s microprogrammed Control Unit, Examples on microprograms
Module Memory Organization consists of the following subtopics Classifications of primary and secondary memories. Types of RAM (SRAM, DRAM, SDRAM, DDR, SSD) and ROM, Characteristics of memory, Memory hierarchy: cost and performance measurement. Virtual Memory: Concept, Segmentation and Paging, Address translation mechanism. Interleaved and Associative memory. Cache memory Concepts, Locality of reference, design problems based on mapping techniques. Cache Coherency, Write Policies. Module I/O Organization and Peripherals consists of the following subtopics Common I/O device types and characteristics, Types of data transfer techniques: Programmed I/O, Interrupt driven I/O and DMA. Introduction to buses, Bus arbitration and multiple bus hierarchy, Interrupt types, Interrupts handling Module Advanced Processor Principles consists of the following subtopics Introduction to parallel processing, Flynn‟s Classification, Concepts of superscalar architecture, out-of-order execution, speculative execution, multithreaded processor, VLIW, data flow computing. Introduction to Multi-core processor architecture.
Suggested Text Books for the subjects Computer Organization and Architecture by Mumbai university are as follows William Stallings, “Computer Organization and Architecture: Designing for Performance”, Pearson Publication, 10th Edition, 2013 . John P. Hayes, “Computer Architecture and Organization”, McGraw-Hill, 1988 B. Govindarajulu, “Computer Architecture and Organization: Design Principles and Applications”, Second Edition, McGraw-Hill (India). Suggested Reference Books for the subjects Computer Organization and Architecture by Mumbai University are as follows Andrew S. Tanenbaum “Structured Computer Organization”, Pearson, Sixth Edition. Morris Mano. “Computer System Architecture” Pearson Publication, 3rd Edition, 2007. Kai Hwang, Fayé Alayé Briggs. “Computer architecture and parallel processing”, McGraw-Hill . P. Pal Chaudhuri. “Computer Organization and Design” Prentice Hall India, 2004 Dr. M. Usha, T.S. Shrikant. “Computer System Architecture and Organization” Wiley India, 2014.
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- Lectures 48
- Quizzes 0
- Duration 10 hours
- Skill level All levels
- Language Hindi
- Students 4385
- Certificate No
- Assessments Yes