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[MCQs] Microprocessor

Module 01

1. The instruction that is used to transfer the data from source operand to destination operand is

a) data copy/transfer instruction

b) branch instruction

c) arithmetic/logical instruction

d) string instruction

Answer: a

Explanation: These instructions are used to copy and transfer the instructions.

 

2. Which of the following is not a data copy/transfer instruction?

a) MOV

b) PUSH

c) DAS

d) POP

Answer: c

Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.

 

3. The instructions that involve various string manipulation operations are

a) branch instructions

b) flag manipulation instructions

c) shift and rotate instructions

d) string instructions

Answer: d

Explanation: The string instructions perform operations on strings such as load, move, scan, compare etc.

 

4. Which of the following instruction is not valid?

a) MOV AX, BX

b) MOV DS, 5000H

c) MOV AX, 5000H

d) PUSH AX

Answer: b

Explanation: Both the source and destination operands cannot be memory locations except for string instructions.

 

5. In PUSH instruction, after each execution of the instruction, the stack pointer is

a) incremented by 1

b) decremented by 1

c) incremented by 2

d) decremented by 2

Answer: d

Explanation: The actual current stack-top is always occupied by the previously pushed data. So, the push operation decrements SP by 2 and then stores the two bytes contents of the operand onto the stack.

 

6. The instruction that pushes the contents of the specified register/memory location on to the stack is

a) PUSHF

b) POPF

c) PUSH

d) POP

Answer: c

Explanation: Since PUSH operation transfers data to stack from a register or memory location.

 

7. In POP instruction, after each execution of the instruction, the stack pointer is

a) incremented by 1

b) decremented by 1

c) incremented by 2

d) decremented by 2

Answer: c

Explanation: The actual current stack top is poped into the specific operand as the contents of stack top memory is stored in AL&SP and further contents of the memory location pointed to by SP are copied to AH & SP.

 

8. The instructions that are used for reading an input port and writing an output port respectively are

a) MOV, XCHG

b) MOV, IN

c) IN, MOV

d) IN, OUT

Answer: d

Explanation: The address of the input/output port may be specified directly or indirectly.

Example for input port: IN AX, DX; This instruction reads data from a 16-bit port whose address is in DX and stores it in AX

Example for output port: OUT 03H, AL; This sends data available in AL to a port whose address is 03H.

 

9. The instruction that is used for finding out the codes in case of code conversion problems is

a) XCHG

b) XLAT

c) XOR

d) JCXZ

Answer: b

Explanation: The translate(XLAT) instruction is used to find codes.

 

10. The instruction that loads effective address formed by destination operand into the specified source register is

a) LEA

b) LDS

c) LES

d) LAHF

Answer: a

Explanation: The instruction, LEA loads effective address and is more useful for assembly language rather than for machine language.

 

11. The instruction that loads the AH register with the lower byte of the flag register is

a) SAHF

b) AH

c) LAHF

d) PUSHF

Answer: c

Explanation: The instruction LAHF(Load AH from a lower byte of Flag) may be used to observe the status of all the condition code flags(except overflow flag) at a time.

 

12. The instruction that pushes the flag register on to the stack is

a) PUSH

b) POP

c) PUSHF

d) POPF

Answer: c

Explanation: The instruction PUSHF(push flags to stack) pushes the flag register on to the stack.

 

13. The instruction that loads the flag register completely from the word contents of the memory location is

a) PUSH

b) POP

c) PUSHF

d) POPF

Answer: d

Explanation: POPF is pop flags to stack.

 

14. The instruction that adds immediate data/contents of the memory location specified in an instruction/register to the contents of another register/memory location is

a) SUB

b) ADD

c) MUL

d) DIV

Answer: b

Explanation: ADD instruction adds the data.

 

15. The instruction that supports addition when carry exists is

a) ADD

b) ADC

c) ADD & ADC

d) None of the mentioned

Answer: b

Explanation: ADC(Add with Carry) instruction performs the same operation as ADD operation, but adds the carry flag bit to the result.

 

16. If an interrupt is generated from outside the processor then it is an

a) internal interrupt

b) external interrupt

c) interrupt

d) none of the mentioned

Answer: b

Explanation: If an external device or a signal interrupts the processor from outside then it is an external interrupt.

 

17. If the interrupt is generated by the execution of an interrupt instruction then it is

a) internal interrupt

b) external interrupt

c) interrupt-in-interrupt

d) none of the mentioned

Answer: a

Explanation: The internal interrupt is generated internally by the processor circuit or by the execution of an interrupt instruction.

 

18. Example of an external interrupt is

a) divide by zero interrupt

b) keyboard interrupt

c) overflow interrupt

d) type2 interrupt

Answer: b

Explanation: Since the keyboard is external to the processor, it is an external interrupt.

 

19. Example of an internal interrupt is

a) divide by zero interrupt

b) overflow interrupt

c) interrupt due to INT

d) all of the mentioned

Answer: d

Explanation: Since the interrupts occur within the processor itself, they are called internal interrupts.

 

20. The interrupt request that is independent of IF flag is

a) NMI

b) TRAP

c) Divide by zero

d) All of the mentioned

Answer: d

Explanation: These requests are independent of IF flag.

 

21. The type of the interrupt may be passed to the interrupt structure of CPU from

a) interrupt service routine

b) stack

c) interrupt controller

d) none of the mentioned

Answer: c

Explanation: After an interrupt is acknowledged, the CPU computes the vector address from the type of the interrupt that may be passed to the internal structure of the CPU from an interrupt controller in case of external interrupts.

 

22. During the execution of an interrupt, the data pushed into the stack is the content of

a) IP

b) CS

c) PSW

d) All of the mentioned

Answer: d

Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.

 

23. After every response to the single step interrupt the flag that is cleared is

a) IF (Interrupt Flag)

b) TF (Trap Flag)

c) OF (Overflow Flag)

d) None of the mentioned

Answer: b

Explanation: If the trap flag is set then the processor enters the single step execution mode. After the execution, the trap flag is cleared.

 

24. At the end of ISR, the instruction should be

a) END

b) ENDS

c) IRET

d) INTR

Answer: c

Explanation: After the execution of the ISR, the control must go to the previous program (maybe main program) which was being executed. To execute it, IRET is placed at the end of ISR.

 

25. When the CPU executes IRET,

a) contents of IP and CS are retrieved

b) the control transfers from ISR to main program

c) clears the trap flag

d) clears the interrupt flag

Answer: a

Explanation: When the instruction IRET is executed, the contents of flags, IP and CS which were saved at the stack by the CALL instruction are retrieved to the respective registers.

 

26. The stack pointer register contains

a) address of the stack segment

b) pointer address of the stack segment

c) offset of address of stack segment

d) data present in the stack segment

Answer: c

Explanation: The stack pointer register contains the offset of the address of the stack segment.

 

27. The stack segment register contains

a) address of the stack segment

b) base address of the stack segment

c) pointer address of the stack segment

d) data in the stack segment

Answer: b

Explanation: The stack segment register contains base address of the stack segment in the memory. The stack pointer register (sP) and stack segment register (SS) together address the stack-top.

 

28. PUSH operation

a) decrements SP

b) increments SP

c) decrements SS

d) increments SS

Answer: a

Explanation: Each PUSH operation decrements the SP ( Stack Pointer) register.

 

29. POP operation

a) decrements SP

b) increments SP

c) decrements SS

d) increments SS

Answer: b

Explanation: Each POP operation increments the SP ( Stack Pointer) register.

 

30. The register or memory location that is pushed into the stack at the end must be

a) popped off last

b) pushed off first

c) popped off first

d) pushed off last

Answer: c

Explanation: The data can be retrieved by POP operation and as in stack, the data that is pushed at the end must be popped off first.

 

31. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK

the ASSUME directive directs to the assembler the

a) address of the stack segment

b) pointer address of the stack segment

c) name of the stack segment

d) name of the stack, code and data segments

Answer: d

Explanation: The directive ASSUME facilitates to name the segments with the desired name that is not a mnemonic or keyword.

 

32. When a stack segment is initialised then

a) SS and SP are initialised

b) only SS is initialised

c) only SP is initialised

d) SS and SP need not be initialised

Answer: a

Explanation: Though the Stack segment is initialised, the SS and SP pointers must be initialised.

 

33. The number of PUSH instructions and POP instructions in a subroutine must be

a) PUSH instructions must be greater than POP instructions

b) POP instructions must be greater than PUSH instructions

c) Both must be equal

d) Instructions may be any kind

Answer: c

Explanation: The number of PUSH instructions must be equal to the number of POP instructions.

 

34. 8086 does not support

a) Arithmetic operations

b) logical operations

c) BCD operations

d) Direct BCD packed multiplication

Answer: d

Explanation: The 8086 microprocessor does not support direct BCD packed operations.

 

35. For 8086 microprocessor, the stack segment may have a memory block of a maximum of

a) 32K bytes

b) 64K bytes

c) 16K bytes

d) NONE

Answer: b

Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K bytes.

 

36. The bit that indicates whether the segment has been accessed by the CPU or not is

a) base address

b) attribute bit

c) present bit

d) granular bit

Answer: b

Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been accessed by the CPU or not.

 

37. The TYPE field of a descriptor is used to find the

a) descriptor type

b) segment type

c) descriptor and segment type

d) none

Answer: c

Explanation: The type field decides the descriptor type and hence the segment type.

 

38. If the segment descriptor bit, S=0, then the descriptor is

a) data segment descriptor

b) code segment descriptor

c) system descriptor

d) all of the mentioned

Answer: c

Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.

 

39. The bit that indicates whether the segment is page addressable is

a) base address

b) attribute bit

c) present bit

d) granularity bit

Answer: d

Explanation: The granularity bit indicates whether the segment is page addressable.

 

40. If the Default operation size bit, D=1, the code segment operation size selected is

a) 8-bit

b) 16-bit

c) 32-bit

d) 64-bit

Answer: c

Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand segment.

 

41. The segment descriptor contains

a) access rights

b) limit

c) base address

d) all of the mentioned

Answer: d

Explanation: The segment descriptors are 8-byte quantities containing access right or attribute bits along with the base and limit of the segments.

 

42. Which of the following is not a type of segment descriptor?

a) system descriptors

b) local descriptors

c) gate descriptors

d) none

Answer: d

Explanation: The five types of segment descriptors of 80386 are:

Code or data segment descriptors

System descriptors

Local descriptors

TSS(task state segment) descriptors

Gate descriptors.

 

43. The limit field of the descriptor is of

a) 10 bits

b) 8 bits

c) 16 bits

d) 20 bits

Answer: d

Explanation: The limit field of the descriptor is of 20 bits.

 

44. The starting address of the segment in physical memory is decided by

a) physical memory

b) segment descriptors

c) operating system

d) base address

Answer: c

Explanation: The base address that marks the starting address of the segment in physical memory is decided by the operating system and is of 32 bits.

 

45. The total descriptors that the 80386 can handle is

a) 2K

b) 8K

c) 4K

d) 16K

Answer: d

Explanation: 80386 can handle total 16K descriptors and hence segments.

Module 02

1. The instruction, MOV AX, 0005H belongs to the address mode

a) register

b) direct

c) immediate

d) register relative

Answer: c

Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears in the form of successive byte or bytes.

 

2. The instruction, MOV AX, 1234H is an example of

a) register addressing mode

b) direct addressing mode

c) immediate addressing mode

d) based indexed addressing mode

Answer: c

Explanation: Since immediate data is present in the instruction.

 

3. The instruction, MOV AX, [2500H] is an example of

a) immediate addressing mode

b) direct addressing mode

c) indirect addressing mode

d) register addressing mode

Answer: b

Explanation: Since the address is directly specified in the instruction as a part of it.

 

4. If the data is present in a register and it is referred using the particular register, then it is

a) direct addressing mode

b) register addressing mode

c) indexed addressing mode

d) immediate addressing mode

Answer: b

Explanation: Since register is used to refer the address.

 

5. The instruction, MOV AX,[BX] is an example of

a) direct addressing mode

b) register addressing mode

c) register relative addressing mode

d) register indirect addressing mode

Answer: d

Explanation: Since the register used to refer to the address is accessed indirectly.

 

6. If the offset of the operand is stored in one of the index registers, then it is

a) based indexed addressing mode

b) relative based indexed addressing mode

c) indexed addressing mode

d) none of the mentioned

Answer: c

Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest of them, address is stored.

 

7. The addressing mode that is used in unconditional branch instructions is

a) intrasegment direct addressing mode

b) intrasegment indirect addressing mode

c) intrasegment direct and indirect addressing mode

d) intersegment direct addressing mode

Answer: b

Explanation: In intrasegment indirect mode, the branch address is found as the content of a register or a memory location.

 

8. If the location to which the control is to be transferred lies in a different segment other than the current one, then the mode is called

a) intrasegment mode

b) intersegment direct mode

c) intersegment indirect mode

d) intersegment direct and indirect mode

Answer: d

Explanation: In intersegment mode, the control to be transferred lies in a different segment.

 

9. The instruction, JMP 5000H:2000H;

is an example of

a) intrasegment direct mode

b) intrasegment indirect mode

c) intersegment direct mode

d) intersegment indirect mode

Answer: c

Explanation: Since in intersegment direct mode, the address to which the control is to be transferred is in a different segment.

 

10. The contents of a base register are added to the contents of index register in

a) indexed addressing mode

b) based indexed addressing mode

c) relative based indexed addressing mode

d) based indexed and relative based indexed addressing mode

Answer: d

Explanation: The effective address is formed by adding the contents of both base and index registers to a default segment.

 

11. The instruction that is used to transfer the data from source operand to destination operand is

a) data copy/transfer instruction

b) branch instruction

c) arithmetic/logical instruction

d) string instruction

Answer: a

Explanation: These instructions are used to copy and transfer the instructions.

 

12. Which of the following is not a data copy/transfer instruction?

a) MOV

b) PUSH

c) DAS

d) POP

Answer: c

Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.

 

13. The instructions that involve various string manipulation operations are

a) branch instructions

b) flag manipulation instructions

c) shift and rotate instructions

d) string instructions

Answer: d

Explanation: The string instructions perform operations on strings such as load, move, scan, compare etc.

 

14. Which of the following instruction is not valid?

a) MOV AX, BX

b) MOV DS, 5000H

c) MOV AX, 5000H

d) PUSH AX

Answer: b

Explanation: Both the source and destination operands cannot be memory locations except for string instructions.

 

15. In PUSH instruction, after each execution of the instruction, the stack pointer is

a) incremented by 1

b) decremented by 1

c) incremented by 2

d) decremented by 2

Answer: d

Explanation: The actual current stack-top is always occupied by the previously pushed data. So, the push operation decrements SP by 2 and then stores the two bytes contents of the operand onto the stack.

 

16. The instruction that pushes the contents of the specified register/memory location on to the stack is

a) PUSHF

b) POPF

c) PUSH

d) POP

Answer: c

Explanation: Since PUSH operation transfers data to stack from a register or memory location.

 

17. In POP instruction, after each execution of the instruction, the stack pointer is

a) incremented by 1

b) decremented by 1

c) incremented by 2

d) decremented by 2

Answer: c

Explanation: The actual current stack top is poped into the specific operand as the contents of stack top memory is stored in AL&SP and further contents of the memory location pointed to by SP are copied to AH & SP.

 

18. The instructions that are used for reading an input port and writing an output port respectively are

a) MOV, XCHG

b) MOV, IN

c) IN, MOV

d) IN, OUT

Answer: d

Explanation: The address of the input/output port may be specified directly or indirectly.

Example for input port: IN AX, DX; This instruction reads data from a 16-bit port whose address is in DX and stores it in AX

Example for output port: OUT 03H, AL; This sends data available in AL to a port whose address is 03H.

 

19. The instruction that is used for finding out the codes in case of code conversion problems is

a) XCHG

b) XLAT

c) XOR

d) JCXZ

Answer: b

Explanation: The translate(XLAT) instruction is used to find codes.

 

20. The instruction that loads effective address formed by destination operand into the specified source register is

a) LEA

b) LDS

c) LES

d) LAHF

Answer: a

Explanation: The instruction, LEA loads effective address and is more useful for assembly language rather than for machine language.

 

21. The instruction that loads the AH register with the lower byte of the flag register is

a) SAHF

b) AH

c) LAHF

d) PUSHF

Answer: c

Explanation: The instruction LAHF(Load AH from a lower byte of Flag) may be used to observe the status of all the condition code flags(except overflow flag) at a time.

 

22. The instruction that pushes the flag register on to the stack is

a) PUSH

b) POP

c) PUSHF

d) POPF

Answer: c

Explanation: The instruction PUSHF(push flags to stack) pushes the flag register on to the stack.

 

23. The instruction that loads the flag register completely from the word contents of the memory location is

a) PUSH

b) POP

c) PUSHF

d) POPF

Answer: d

Explanation: POPF is pop flags to stack.

 

24. The instruction that adds immediate data/contents of the memory location specified in an instruction/register to the contents of another register/memory location is

a) SUB

b) ADD

c) MUL

d) DIV

Answer: b

Explanation: ADD instruction adds the data.

 

25. The instruction that supports addition when carry exists is

a) ADD

b) ADC

c) ADD & ADC

d) None of the mentioned

Answer: b

Explanation: ADC(Add with Carry) instruction performs the same operation as ADD operation, but adds the carry flag bit to the result.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Segmentation”.

 

26. The instruction, “INC” increases the contents of the specified register or memory location by

a) 2

b) 0

c) 1

d) 3

Answer: c

Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.

 

27. The instruction that subtracts 1 from the contents of the specified register/memory location is

a) INC

b) SUBB

c) SUB

d) DEC

Answer: d

Explanation: The DEC instruction decrements the contents of a specified register/memory location by 1.

 

28. The instruction that enables subtraction with borrow is

a) DEC

b) SUB

c) SBB

d) None of the mentioned

Answer: c

Explanation: The SBB instruction subtracts the source operand and the borrow flag from the destination operand.

 

29. The flag that acts as Borrow flag in the instruction, SBB is

a) direction flag

b) carry flag

c) parity flag

d) trap flag

Answer: b

Explanation: If borrow exists in the subtraction operation performed then carry flag is set.

 

30. In general, the source operand of an instruction can be

a) memory location

b) register

c) immediate data

d) all of the mentioned

Answer: d

Explanation: The source operand is the element which is data or data stored memory location on which operation is performed.

 

31. In general, the destination operand of an instruction can be

a) memory location

b) register

c) immediate data

d) memory location and register

Answer: d

Explanation: Since the destination should be able to store the data, immediate data cannot be considered as a destination operand.

 

32. The instruction, CMP to compare source and destination operands it performs

a) addition

b) subtraction

c) division

d) multiplication

Answer: b

Explanation: For comparison, the instruction CMP subtracts source operand from destination operand.

 

33. During comparison operation, the result of comparing or subtraction is stored in

a) memory

b) registers

c) stack

d) no where

Answer: d

Explanation: The result of subtraction operation is not stored anywhere during a comparison.

 

34. The instruction that converts the result in an unpacked decimal digits is

a) AAA

b) AAS

c) AAM

d) All of the mentioned

Answer: d

Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are called as “Unpacked BCD arithmetic instructions”.

 

35. Which of the following is a mnemonic?

a) ADD

b) ADC

c) AAA

d) ADD & ADC

Answer: c

Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.

 

36. The instruction in which adjustment is made before performing the operation is

a) AAA

b) AAS

c) AAM

d) AAD

Answer: d

Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before dividing the two unpacked BCD digits.

 

37. The expansion of DAA is

a) decimal adjust after addition

b) decimal adjust before addition

c) decimal adjust accumulator

d) decimal adjust auxiliary

Answer: c

Explanation: This instruction performs conversion operation.

 

38. The instruction that is used to convert the result of the addition of two packed BCD numbers to a valid BCD number is

a) DAA

b) DAS

c) AAA

d) AAS

Answer: a

Explanation: In this conversion, the result has to be only in AL.

 

39. The ROR instruction rotates the contents of the destination operand to

a) left

b) right

c) left and then right

d) right and then left

Answer: b

Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.

 

40. The instruction, “INC” increases the contents of the specified register or memory location by

a) 2

b) 0

c) 1

d) 3

Answer: c

Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.

 

41. The instruction that subtracts 1 from the contents of the specified register/memory location is

a) INC

b) SUBB

c) SUB

d) DEC

Answer: d

Explanation: The DEC instruction decrements the contents of a specified register/memory location by 1.

 

42. The instruction that enables subtraction with borrow is

a) DEC

b) SUB

c) SBB

d) None of the mentioned

Answer: c

Explanation: The SBB instruction subtracts the source operand and the borrow flag from the destination operand.

 

43. The flag that acts as Borrow flag in the instruction, SBB is

a) direction flag

b) carry flag

c) parity flag

d) trap flag

Answer: b

Explanation: If borrow exists in the subtraction operation performed then carry flag is set.

 

44. In general, the source operand of an instruction can be

a) memory location

b) register

c) immediate data

d) all of the mentioned

Answer: d

Explanation: The source operand is the element which is data or data stored memory location on which operation is performed.

 

45. In general, the destination operand of an instruction can be

a) memory location

b) register

c) immediate data

d) memory location and register

Answer: d

Explanation: Since the destination should be able to store the data, immediate data cannot be considered as a destination operand.

 

46. The instruction, CMP to compare source and destination operands it performs

a) addition

b) subtraction

c) division

d) multiplication

Answer: b

Explanation: For comparison, the instruction CMP subtracts source operand from destination operand.

 

47. During comparison operation, the result of comparing or subtraction is stored in

a) memory

b) registers

c) stack

d) no where

Answer: d

Explanation: The result of subtraction operation is not stored anywhere during a comparison.

 

48. The instruction that converts the result in an unpacked decimal digits is

a) AAA

b) AAS

c) AAM

d) All of the mentioned

Answer: d

Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are called as “Unpacked BCD arithmetic instructions”.

 

49. Which of the following is a mnemonic?

a) ADD

b) ADC

c) AAA

d) ADD & ADC

Answer: c

Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.

 

50. The instruction in which adjustment is made before performing the operation is

a) AAA

b) AAS

c) AAM

d) AAD

Answer: d

Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before dividing the two unpacked BCD digits.

 

51. The expansion of DAA is

a) decimal adjust after addition

b) decimal adjust before addition

c) decimal adjust accumulator

d) decimal adjust auxiliary

Answer: c

Explanation: This instruction performs conversion operation.

 

52. The instruction that is used to convert the result of the addition of two packed BCD numbers to a valid BCD number is

a) DAA

b) DAS

c) AAA

d) AAS

Answer: a

Explanation: In this conversion, the result has to be only in AL.

 

53. The ROR instruction rotates the contents of the destination operand to

a) left

b) right

c) left and then right

d) right and then left

Answer: b

Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.

 

54. The mnemonic that is placed before the arithmetic operation is performed is

a) AAA

b) AAS

c) AAM

d) AAD

Answer: d

Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL.

 

55. The Carry flag is undefined after performing the operation

a) AAA

b) ADC

c) AAM

d) AAD

Answer: d

Explanation: Since the operation, AAD is performed before division operation is performed, the carry flag, auxiliary flag and overflow flag are undefined.

 

56. The instruction that performs logical AND operation and the result of the operation is not available is

a) AAA

b) AND

c) TEST

d) XOR

Answer: c

Explanation: In the TEST instruction, the logical AND operation is performed and the result is not stored but flags are affected.

 

57. In the RCL instruction, the contents of the destination operand undergo function as

a) carry flag is pushed into LSB & MSB is pushed into the carry flag

b) carry flag is pushed into MSB & LSB is pushed into the carry flag

c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag

d) parity flag is pushed into MSB & LSB is pushed into the carry flag

Answer: a

Explanation: In RCL(Rotate right through carry), for each operation, the carry flag is pushed into LSB and the MSB of the operand is pushed into carry flag.

58. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX register becomes zero is

a) SCAS

b) REP

c) CMPS

d) STOS

Answer: b

Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX register becomes zero. When CX becomes zero, the execution proceeds to the next instruction in sequence.

59. Match the following

A) MOvSB/SW       1) loads AL/AX register by content of a string

B) CMPS           2) moves a string of bytes stored in source to destination

C) SCAS           3) compares two strings of bytes or words whose length is stored in CX register

D) LODS           4) scans a string of bytes or words

a) A-3,B-4,C-2,D-1

b) A-2,B-1,C-4,D-3

c) A-2,B-3,C-1,D-4

d) A-2,B-3,C-4,D-1

Answer: d

Explanation: By using the string instructions, the operations on strings can be performed.

 

60. The instructions that are used to call a subroutine from the main program and return to the main program after execution of called function are

a) CALL, JMP

b) JMP, IRET

c) CALL, RET

d) JMP, RET

Answer: c

Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the stack, before the control is transferred to the procedure. At the end of the procedure, the RET instruction must be executed to retrieve the stored contents of IP & CS registers from a stack.

 

61. The instruction that unconditionally transfers the control of execution to the specified address is

a) CALL

b) JMP

c) RET

d) IRET

Answer: b

Explanation: In this the control transfers to the address specified in the instruction and flags are not affected by this instruction.

 

62. Which instruction cannot force the 8086 processor out of ‘halt’ state?

a) Interrupt request

b) Reset

c) Both interrupt request and reset

d) Hold

Answer: d

Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of the ‘halt’ state.

 

63. NOP instruction introduces

a) Address

b) Delay

c) Memory location

d) None of the mentioned

Answer: b

Explanation: NOP is the No operation. It means that the processor performs no operation for the clock cycle and thus there exists a delay.

 

64. Which of the following is not a machine controlled instruction?

a) HLT

b) CLC

c) LOCK

d) ESC

Answer: b

Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry Flag.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Assembler Directives and Operators”.

 

65. The assembler directives which are the hints using some predefined alphabetical strings are given to

a) processor

b) memory

c) assembler

d) processor & assembler

Answer: c

Explanation: These directives help the assembler to correctly understand the assembly language programs to prepare the codes.

 

66. The directive used to inform the assembler, the names of the logical segments to be assumed for different segments used in the program is

a) ASSUME

b) SEGMENT

c) SHORT

d) DB

Answer: a

Explanation: In ALP, each segment is given a name by using the directive ASSUME

SYNTAX: ASSUME segment:segment_name

Eg: ASSUME CS:Code

here CS is the Code segment and code is the name assumed to the segment.

 

67. Match the following

a) DB          1) used to direct the assembler to reserve only 10-bytes

b) DT          2) used to direct the assembler to reserve only 4 words

c) DW          3) used to direct the assembler to reserve byte or bytes

d) DQ          4) used to direct the assembler to reserve words

a) a-3, b-2, c-4, d-1

b) a-2, b-3, c-1, d-4

c) a-3, b-1, c-2, d-4

d) a-3, b-1, c-4, d-2

Answer: d

Explanation: These directives are used for allocating memory locations in the available memory.

 

68. The directive that marks the end of an assembly language program is

a) ENDS

b) END

c) ENDS & END

d) None of the mentioned

Answer: b

Explanation: The directive END is used to denote the completion of the program.

 

69. The directive that marks the end of a logical segment is

a) ENDS

b) END

c) ENDS & END

d) None of the mentioned

Answer: a

Explanation: The directive ENDS is used to end a segment where as the directive END is used to end the program.

 

70. The directive that updates the location counter to the next even address while executing a series of instructions is

a) EVN

b) EVEN

c) EVNE

d) EQU

Answer: b

Explanation: The directive updates location counter to next even address if the current location counter contents are not even.

 

71. The directive that directs the assembler to start the memory allotment for a particular segment/block/code from the declared address is

a) OFFSET

b) LABEL

c) ORG

d) GROUP

Answer: c

Explanation: If an ORG is written then the assembler initiates the location counter to keep the track of allotted address for the module as mentioned in the directive.

If the directive is not present, then the location counter is initialized to 0000H.

 

72. The directive that marks the starting of the logical segment is

a) SEG

b) SEGMENT

c) SEG & SEGMENT

d) PROC

Answer: b

Explanation: The directive SEGMENT indicates the beginning of the segment.

 

73. The recurrence of the numerical values or constants in a program code is reduced by

a) ASSUME

b) LOCAL

c) LABEL

d) EQU

Answer: d

Explanation: In this, the recurring/repeating value is assigned with a label. The label is placed instead of the numerical value in the entire program code.

 

74. The labels or constants that can be used by any module in the program is possible when they are declared as

a) PUBLIC

b) LOCAL

c) GLOBAL

d) Either PUBLIC or GLOBAL

Answer: c

Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used by any module in the program.

 

75. If a number of instructions are repeating through the main program, then to reduce the length of the program, __________ is used.

a) procedure

b) subroutine

c) macro

d) none of the mentioned

Answer: c

Explanation: For a certain number of instructions that are repeated in the main program, when macro is defined then the code of a program is reduced by placing the name of the macro at which the set of instructions are needed to be repeated.

 

76. The process of assigning a label or macroname to the string is called

a) initialising macro

b) initialising string macro

c) defining a string macro

d) defining a macro

Answer: d

Explanation: The process of assigning a label to the string is called defining a macro.

 

77. A macro within a macro is called

a) macro-within-macro

b) nested macro

c) macro-in-macro

d) none of the mentioned

Answer: b

Explanation: A macro may be called from inside a macro. This type of macro is called nested macro.

 

78. A macro can be defined as

a) beginning of a program

b) end of a program

c) after initialisation of program

d) anywhere in a program

Answer: d

Explanation: A macro can be defined anywhere in a program.

 

79. A macro can be used as ________

a) in data segment

b) to represent directives

c) to represent statements

d) all of the mentioned

Answer: d

Explanation: A macro may be used in data segment and can also be used to represent statements and directives.

 

80. The end of a macro can be represented by the directive.

a) END

b) ENDS

c) ENDM

d) ENDD

Answer: c

Explanation: The ENDM directive marks the end of the instructions or statements sequence assigned with the macro name.

 

81. Inserting the statements and instructions represented by macro, directly at the place of the macroname, in the program, is known as

a) calling a macro

b) inserting a macro

c) initializing a macro

d) none of the mentioned

Answer: a

Explanation: Inserting the statements and instructions at the place of macroname, in the program, is known as calling a macro.

 

82. The time required for execution of a macro is ________ that of the procedure.

a) greater than

b) less than

c) equal to

d) none of the mentioned

Answer: b

Explanation: The time required for execution of a macro is less than that of procedure as it does not contain CALL and RET instructions as the procedures do.

 

83. Which of the following statements is incorrect?

a) complete code of instruction string is inserted at each place, wherever the macroname appears

b) macro requires less time of execution than that of procedure

c) macro uses stack memory

d) macroname can be anything except registers and mnemonics

Answer: c

Explanation: Macro does not require stack memory and hence has less time for execution.

 

84. The beginning of the macro can be represented as

a) START

b) BEGIN

c) MACRO

d) None of the mentioned

Answer: c

Explanation: The beginning of the macro is represented as macroname followed by the directive MACRO.

SYNTAX: macroname MACRO

EXAMPLE: STRINGS MACRO.

Module 03

1. If an interrupt is generated from outside the processor then it is an

a) internal interrupt

b) external interrupt

c) interrupt

d) none of the mentioned

Answer: b

Explanation: If an external device or a signal interrupts the processor from outside then it is an external interrupt.

 

2. If the interrupt is generated by the execution of an interrupt instruction then it is

a) internal interrupt

b) external interrupt

c) interrupt-in-interrupt

d) none of the mentioned

Answer: a

Explanation: The internal interrupt is generated internally by the processor circuit or by the execution of an interrupt instruction.

 

3. Example of an external interrupt is

a) divide by zero interrupt

b) keyboard interrupt

c) overflow interrupt

d) type2 interrupt

Answer: b

Explanation: Since the keyboard is external to the processor, it is an external interrupt.

 

4. Example of an internal interrupt is

a) divide by zero interrupt

b) overflow interrupt

c) interrupt due to INT

d) all of the mentioned

Answer: d

Explanation: Since the interrupts occur within the processor itself, they are called internal interrupts.

 

5. The interrupt request that is independent of IF flag is

a) NMI

b) TRAP

c) Divide by zero

d) All of the mentioned

Answer: d

Explanation: These requests are independent of IF flag.

 

6. The type of the interrupt may be passed to the interrupt structure of CPU from

a) interrupt service routine

b) stack

c) interrupt controller

d) none of the mentioned

Answer: c

Explanation: After an interrupt is acknowledged, the CPU computes the vector address from the type of the interrupt that may be passed to the internal structure of the CPU from an interrupt controller in case of external interrupts.

 

7. During the execution of an interrupt, the data pushed into the stack is the content of

a) IP

b) CS

c) PSW

d) All of the mentioned

Answer: d

Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.

 

8. After every response to the single step interrupt the flag that is cleared is

a) IF (Interrupt Flag)

b) TF (Trap Flag)

c) OF (Overflow Flag)

d) None of the mentioned

Answer: b

Explanation: If the trap flag is set then the processor enters the single step execution mode. After the execution, the trap flag is cleared.

 

9. At the end of ISR, the instruction should be

a) END

b) ENDS

c) IRET

d) INTR

Answer: c

Explanation: After the execution of the ISR, the control must go to the previous program (maybe main program) which was being executed. To execute it, IRET is placed at the end of ISR.

 

10. When the CPU executes IRET,

a) contents of IP and CS are retrieved

b) the control transfers from ISR to main program

c) clears the trap flag

d) clears the interrupt flag

Answer: a

Explanation: When the instruction IRET is executed, the contents of flags, IP and CS which were saved at the stack by the CALL instruction are retrieved to the respective registers.

 

11. The number of hardware interrupts that the processor 8085 consists of is

a) 1

b) 3

c) 5

d) 7

Answer: c

Explanation: The processor 8085 has five hardware interrupt pins. Out of these five, four pins were alloted fixed vector addresses but the pin INTR was not alloted by vector address, rather an external device was supposed to hand over the type of the interrupt to the microprocessor.

 

12. The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is

a) Interrupt Request Register

b) In-Service Register

c) Priority resolver

d) Interrupt Mask Register

Answer: a

Explanation: The interrupts at IRQ input lines are handled by Interrupt Request Register internally.

 

13. The register that stores the bits required to mask the interrupt inputs is

a) In-service register

b) Priority resolver

c) Interrupt Mask register

d) None

Answer: c

Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request Register) at the direction of the Priority Resolver.

 

14. The interrupt control logic

a) manages interrupts

b) manages interrupt acknowledge signals

c) accepts interrupt acknowledge signal

d) all of the mentioned

Answer: d

Explanation: The interrupt control logic performs all the operations that are involved within the interrupts like accepting and managing interrupt acknowledge signals, interrupts.

 

15. In a cascaded mode, the number of vectored interrupts provided by 8259A is

a) 4

b) 8

c) 16

d) 64

Answer: d

Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64 vectored interrupts can be provided.

 

16. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a

a) input to designate chip is master or slave

b) buffer enable

c) buffer disable

d) none

Answer: b

Explanation: When the pin is used in buffered mode, then it can be used as a buffer enable to control buffer transreceivers. If it is not used in buffered mode, then the pin is used as input to designate whether the chip is used as a master or a slave.

 

17. Once the ICW1 is loaded, then the initialization procedure involves

a) edge sense circuit is reset

b) IMR is cleared

c) slave mode address is set to 7

d) all of the mentioned

Answer: d

Explanation: The initialization procedure involves

i) edge sense circuit is reset.

ii) IMR is cleared.

iii) IR7 input is assigned the lowest priority.

iv) slave mode address is set to 7

v) special mask mode is cleared and the status read is set to IRR.

 

18. When non-specific EOI command is issued to 8259A it will automatically

a) set the ISR

b) reset the ISR

c) set the INTR

d) reset the INTR

Answer: b

Explanation: When non-specific EOI command is issued to 8259A it will automatically reset the highest ISR.

 

19. In the application where all the interrupting devices are of equal priority, the mode used is

a) Automatic rotation

b) Automatic EOI mode

c) Specific rotation

d) EOI

Answer: a

Explanation: The automatic rotation is used in the applications where all the interrupting devices are of equal priority.

 

20. Programmable peripheral input-output port is another name for

a) serial input-output port

b) parallel input-output port

c) serial input port

d) parallel output port

Answer: b

Explanation: The parallel input-output port chip 8255 is also known as programmable peripheral input-output port.

 

21. Port C of 8255 can function independently as

a) input port

b) output port

c) either input or output ports

d) both input and output ports

Answer: c

Explanation: Port C can function independently either as input or as output ports.

 

22. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called

a) data bus control

b) read logic control

c) control word register

d) none of the mentioned

Answer: c

Explanation: By programming the bits of control word register, the operations of the ports are specified.

 

23. The data bus buffer is controlled by

a) control word register

b) read/write control logic

c) data bus

d) none of the mentioned

Answer: b

Explanation: The data bus buffer is controlled by read/write control logic.

 

24. The input provided by the microprocessor to the read/write control logic is

a) RESET

b) A1

c) WR(ACTIVE LOW)

d) All of the mentioned

Answer: d

Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs provided by the microprocessor to the read/write control logic of 8255.

 

25. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor is

a) control word register

b) read/write control logic

c) 3-state bidirectional buffer

d) none of the mentioned

Answer: c

Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution of input or output instructions by the microprocessor.

 

26. The port that is used for the generation of handshake lines in mode 1 or mode 2 is

a) port A

b) port B

c) port C Lower

d) port C Upper

Answer: d

Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.

 

27. If A1=0, A0=1 then the input read cycle is performed from

a) port A to data bus

b) port B to data bus

c) port C to data bus

d) CWR to data bus

Answer: b

Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.

 

28. The function, ‘data bus tristated’ is performed when

a) CS(active low) = 1

b) CS(active low) = 0

c) CS(active low) = 0, RD(active low) = 1, WR(active low) = 1

d) CS(active low) = 1 OR CS(active low) = 0, RD(active low) = 1, WR(active low) = 1

Answer: d

Explanation: The data bus is tristated when chip select pin=1 or chip select pin=0 and read and write signals are high i.e 1.

 

29. The pin that clears the control word register of 8255 when enabled is

a) CLEAR

b) SET

c) RESET

d) CLK

Answer: c

Explanation: If reset pin is enabled then the control word register is cleared.

Module 04

1. The number of counters that are present in the programmable timer device 8254 is

a) 1

b) 2

c) 3

d) 4

Answer: c

Explanation: There are three counters that can be used as either counters or delay generators.

 

2. The operation that can be performed on control word register is

a) read operation

b) write operation

c) read and write operations

d) none

Answer: b

Explanation: The control word register can only be written and cannot be read.

 

3. The mode that is used to interrupt the processor by setting a suitable terminal count is

a) mode 0

b) mode 1

c) mode 2

d) mode 3

Answer: a

Explanation: Mode 0 is also called as an interrupt on the terminal count.

 

4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low for

a) 1 clockcycle

b) 2 clockcycles

c) 3 clockcycles

d) 4 clockcycles

Answer: a

Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is reloaded and again the output becomes high and remains so for (N-1) clock pulses.

 

5. The generation of a square wave is possible in the mode

a) mode 1

b) mode 2

c) mode 3

d) mode 4

Answer: c

Explanation: When the count N loaded is even, then for half of the count, the output remains high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse decrements it by 1 resulting in an even count value.

 

6. In control word register, if SC1=0 and SC0=1, then the counter selected is

a) counter 0

b) counter 1

c) counter 2

d) none

Answer: b

Explanation: SC denotes select counter.

 

7. In control word format, if RL1=1, RL0=1 then the operation performed is

a) read/load least significant byte only

b) read/load most significant byte only

c) read/load LSB first and then MSB

d) read/load MSB first and then LSB

Answer: c

Explanation: To access 16 bit, first LSB is loaded first, and then MSB.

 

8. If BCD=0, then the operation is

a) decimal count

b) hexadecimal count

c) binary count

d) octal count

Answer: b

Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.

 

9. The counter starts counting only if

a) GATE signal is low

b) GATE signal is high

c) CLK signal is low

d) CLK signal is high

Answer: b

Explanation: If the GATE signal is enabled, then the counter starts counting.

 

10. The control word register contents are used for

a) initializing the operating modes

b) selection of counters

c) choosing binary/BCD counters

d) all of the mentioned

Answer: d

Explanation: The control word register contents are used for

i) initializing the operating modes (mode 0-mode 4)

ii) selection of counters (counter0-counter2)

iii) choosing binary or BCD counters

iv) loading of the counter registers.

 

11. In direct memory access mode, the data transfer takes place

a) directly

b) indirectly

c) directly and indirectly

d) none of the mentioned

Answer: a

Explanation: In direct memory access mode, the data may transfer directly without the interference from the CPU.

 

12. In 8257 (DMA), each of the four channels has

a) a pair of two 8-bit registers

b) a pair of two 16-bit registers

c) one 16-bit register

d) one 8-bit register

Answer: b

Explanation: The DMA supports four channels, and each of the channels has a pair of two 16-bit registers, namely DMA address register and a terminal count register.

 

13. The common register(s) for all the four channels of 8257 is

a) DMA address register

b) Terminal count register

c) Mode set register and status register

d) None of the mentioned

Answer: c

Explanation: The two common registers for all the four channels of DMA are mode set register and status register.

 

14. In 8257 register format, the selected channel is disabled after the terminal count condition is reached when

a) Auto load is set

b) Auto load is reset

c) TC STOP bit is reset

d) TC STOP bit is set

Answer: d

Explanation: If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is reached, and it further prevents any DMA cycle on the channel.

 

15. The IOR (active low) input line acts as output in

a) slave mode

b) master mode

c) master and slave mode

d) none of the mentioned

Answer: b

Explanation: The IOR (active low) is an active low bidirectional tristate input line, that acts as input in the slave mode, and acts as output in the master mode. In master mode, this signal is used to read data from a peripheral during a memory write cycle.

 

16. The IOW (active low) in its slave mode loads the contents of a data bus to

a) 8-bit mode register

b) upper/lower byte of 16-bit DMA address register

c) terminal count register

d) all of the mentioned

Answer: d

Explanation: In its slave mode, the IOW (active low) loads the contents of a data bus to 8-bit mode register, upper/lower byte of 16-bit DMA address register or terminal count register.

 

17. The pin that disables all the DMA channels by clearing the mode registers is

a) MARK

b) CLEAR

c) RESET

d) READY

Answer: c

Explanation: The RESET pin which is asynchronous input disables all the DMA channels by clearing the mode registers, and tristate all the control lines.

 

18. The pin that requests the access of the system bus is

a) HLDA

b) HRQ

c) ADSTB

d) None of the mentioned

Answer: b

Explanation: The hold request output requests the access of the system bus.

 

19. The pin that is used to write data to the addressed memory location, during DMA write operation is

a) MEMR (active low)

b) AEN

c) MEMW (active low)

d) IOW (active low)

Answer: c

Explanation: The MEMW (active low) is used to write data to the addressed memory location, during DMA write operation.

 

20. The pin that strobes the higher byte of the memory address, generated by the DMA controller into the latches is

a) AEN

b) ADSTB

c) TC

d) None of the mentioned

Answer: b

Explanation: The pin ADSTB strobes the higher byte of the memory address, generated by the DMA controller into the latches.

 

21. In the I/O mode, the 8255 ports work as

a) reset pins

b) set pins

c) programmable I/O ports

d) only output ports

Answer: c

Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.

 

22. In BSR mode, only port C can be used to

a) set individual ports

b) reset individual ports

c) set and reset individual ports

d) programmable I/O ports

Answer: c

Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port bits.

 

23. The feature of mode 0 is

a) any port can be used as input or output

b) output ports are latched

c) maximum of 4 ports are available

d) all of the mentioned

Answer: d

Explanation: In mode 0, any port can be used as input or output and output ports are latched.

 

24. The strobed input/output mode is another name of

a) mode 0

b) mode 1

c) mode 2

d) none

Answer: b

Explanation: In this mode, the handshaking signals control the input or output action of the specified port.

 

25. If the value of the pin STB (Strobe Input) falls to low level, then

a) input port is loaded into input latches

b) input port is loaded into output latches

c) output port is loaded into input latches

d) output port is loaded into output latches

Answer: a

Explanation: If the value of the pin STB (Strobe Input) falls to low level, the input port is loaded into input latches.

 

26. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of

a) Control word register

b) CPU

c) Printer

d) Ports

Answer: c

Explanation: This signal indicates that the printer is selected.

 

27. The pulse width of the signal INIT at the receiving terminal must be more than

a) 10 microseconds

b) 20 microseconds

c) 40 microseconds

d) 50 microseconds

Answer: d

Explanation: The pulse width of the signal must be more than 50microseconds at the receiving terminal.

 

28. The level of the signal ERROR(active low) becomes ‘low’ when the printer is in

a) Paper end state

b) Offline state

c) Error state

d) All of the mentioned

Answer: d

Explanation: The level of the signal ERROR(active low) becomes ‘low’ when the printer is in the Paper end state, Offline state and Error state.

 

29. The signals that are provided to maintain proper data flow and synchronization between the data transmitter and receiver are

a) handshaking signals

b) control signals

c) input signals

d) none

Answer: a

Explanation: Handshaking signals maintain proper data flow and synchronization.

 

30. The feature of mode 2 of 8255 is

a) single 8-bit port is available

b) both inputs and outputs are latched

c) port C is used for generating handshake signals

d) all of the mentioned

Answer: d

Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.

 

31. Programmable peripheral input-output port is another name for

a) serial input-output port

b) parallel input-output port

c) serial input port

d) parallel output port

Answer: b

Explanation: The parallel input-output port chip 8255 is also known as programmable peripheral input-output port.

 

32. Port C of 8255 can function independently as

a) input port

b) output port

c) either input or output ports

d) both input and output ports

Answer: c

Explanation: Port C can function independently either as input or as output ports.

 

33. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called

a) data bus control

b) read logic control

c) control word register

d) none of the mentioned

Answer: c

Explanation: By programming the bits of control word register, the operations of the ports are specified.

 

34. The data bus buffer is controlled by

a) control word register

b) read/write control logic

c) data bus

d) none of the mentioned

Answer: b

Explanation: The data bus buffer is controlled by read/write control logic.

 

35. The input provided by the microprocessor to the read/write control logic is

a) RESET

b) A1

c) WR(ACTIVE LOW)

d) All of the mentioned

Answer: d

Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs provided by the microprocessor to the read/write control logic of 8255.

 

36. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor is

a) control word register

b) read/write control logic

c) 3-state bidirectional buffer

d) none of the mentioned

Answer: c

Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution of input or output instructions by the microprocessor.

 

37. The port that is used for the generation of handshake lines in mode 1 or mode 2 is

a) port A

b) port B

c) port C Lower

d) port C Upper

Answer: d

Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.

 

38. If A1=0, A0=1 then the input read cycle is performed from

a) port A to data bus

b) port B to data bus

c) port C to data bus

d) CWR to data bus

Answer: b

Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.

 

39. The function, ‘data bus tristated’ is performed when

a) CS(active low) = 1

b) CS(active low) = 0

c) CS(active low) = 0, RD(active low) = 1, WR(active low) = 1

d) CS(active low) = 1 OR CS(active low) = 0, RD(active low) = 1, WR(active low) = 1

Answer: d

Explanation: The data bus is tristated when chip select pin=1 or chip select pin=0 and read and write signals are high i.e 1.

 

40. The pin that clears the control word register of 8255 when enabled is

a) CLEAR

b) SET

c) RESET

d) CLK

Answer: c

Explanation: If reset pin is enabled then the control word register is cleared.

Module 05

1. Which of the units is not a part of the internal architecture of 80386?

a) central processing unit

b) memory management unit

c) bus interface unit

d) none of the mentioned

Answer: d

Explanation: The internal architecture of 80386 is divided into three sections namely, central processing unit, memory management unit and bus interface unit.

 

2. The central processing unit has a sub-division of

a) memory unit and control unit

b) memory unit and ALU

c) execution unit and instruction unit

d) execution unit and memory unit

Answer: c

Explanation: The central processing unit is further divided into the execution unit and instruction unit.

 

3. The unit that is used for handling data, and calculates offset address is

a) memory management unit

b) execution unit

c) instruction unit

d) bus interface unit

Answer: b

Explanation: The execution unit has eight general purpose and eight special purpose registers, which are either used for handling the data or calculating the offset addresses.

 

4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is

a) memory management unit

b) execution unit

c) instruction unit

d) barrel shifter

Answer: c

Explanation: The instruction unit decodes the opcode bytes, received from the 16-byte instruction code queue, after decoding them so as to pass it to the control section, for deriving the necessary control signals.

 

5. The unit that increases the speed of all shift and rotate operations is

a) memory management unit

b) execution unit

c) instruction unit

d) barrel shifter

Answer: d

Explanation: The barrel shifter speeds up all shift and rotate operations.

 

6. The memory management unit consists of

a) segmentation unit

b) paging unit

c) segmentation and paging units

d) none of the mentioned

Answer: c

Explanation: The memory management unit consists of a segmentation unit and a paging unit.

 

7. The segmentation unit allows

a) maximum size of 4GB segments

b) use of segment address components

c) use of offset address components

d) all of the mentioned

Answer: d

Explanation: The segmentation unit allows the use of two address components. They are: segment and offset for relocation and sharing of code and data.

 

8. The unit that organizes the physical memory, in terms of pages of 4KB size each is

a) segmentation unit

b) execution unit

c) paging unit

d) instruction unit

Answer: c

Explanation: The paging unit organizes the physical memory, in terms of pages of 4KB size each.

 

9. The paging unit works under the control of

a) memory management unit

b) segmentation unit

c) execution unit

d) instruction unit

Answer: b

Explanation: The paging unit works under the control of the segmentation unit; i.e. each segment is further divided into pages.

 

10. The unit that provides a four level protection mechanism, for system’s code and data against application program is

a) central processing unit

b) segmentation unit

c) bus interface unit

d) none of the mentioned

Answer: b

Explanation: The segmentation unit provides a four level protection mechanism, for protecting and isolating the system’s code and data, from those of the application program.

 

11. The unit that has a prioritizer to resolve the priority of the various bus requests is

a) bus sizing unit

b) data buffer

c) bus control unit

d) execution unit

Answer: c

Explanation: The bus control unit has a prioritizer to resolve the priority of the various bus requests.

 

12. The unit that interfaces the internal data bus with the system bus is

a) bus sizing unit

b) data buffer

c) bus control unit

d) execution unit

Answer: b

Explanation: The data buffer interfaces the internal data bus with the system bus.

 

13. The unit that drives the bus enable and address signals A0-A31 is

a) bus sizing unit

b) bus driving unit

c) address driver

d) bus driver

Answer: c

Explanation: The address driver drives the bus enable and address signals A0-A31.

 

14. Which of the following pin when activated, allows address pipelining?

a) ADS

b) NA

c) AP

d) None of the mentioned

Answer: b

Explanation: The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus cycles.

 

15. The signal that is used to insert WAIT states in a bus cycle in 80386 is

a) HOLD

b) HLDA

c) READY

d) PEREQ

Answer: c

Explanation: READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of slow devices with the CPU.

 

16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is

a) READY

b) NMI

c) HLDA

d) PEREQ

Answer: d

Explanation: The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data word for the coprocessor.

 

17. The pipeline and dynamic bus sizing units handle

a) data signals

b) address signals

c) control signals

d) all of the mentioned

Answer: c

Explanation: The pipeline and dynamic bus sizing units handle the related control signals.

 

18. Which of the following is not a scale factor of addressing modes of 80386?

a) 2

b) 4

c) 6

d) 8

Answer: c

Explanation: In case of the scaled the modes, any of the index register values can be multiplied by a valid scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.

 

19. Contents of an index register are multiplied by a scale factor that may be added further to get the operand offset in

a) base scaled indexed mode

b) scaled indexed mode

c) indexed mode

d) none of the mentioned

Answer: b

Explanation: In scaled indexed mode, contents of an index register are multiplied by a scale factor that may be added further to get the operand offset.

 

20. Contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset in

a) base scaled indexed mode

b) scaled indexed mode

c) indexed mode

d) none of the mentioned

Answer: a

Explanation: In base scaled indexed mode, contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset.

 

21. In the based scaled indexed mode with displacement mode, the contents of an index register are multiplied by a scale factor and are added to

a) base register

b) displacement

c) base register and displacement

d) none of the mentioned

Answer: c

Explanation: Contents of an index register are multiplied by a scale factor and the result is added to a base register and a displacement to get the offset of an operand.

 

22. The following statement of ALP is an example of

MOV EBX, [EDX*4] [ECX].

a) base scaled indexed mode

b) scaled indexed mode

c) indexed mode

d) based scaled indexed mode with displacement mode

Answer: a

Explanation: Since in base scaled indexed mode, contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset.

 

23. The following statement is an example of

MOV EBX, LIST [ESI*2].

MUL ECX, LIST [EBP*4].

a) base scaled indexed mode

b) scaled indexed mode

c) indexed mode

d) based scaled indexed mode with displacement mode

Answer: b

Explanation: Since in scaled indexed mode, contents of an index register are multiplied by a scale factor that may be added further to get the operand offset.

 

24. Bit field can be defined as a group of

a) 8 bits

b) 16 bits

c) 32 bits

d) 64 bits

Answer: c

Explanation: A group of at the most 32 bits(4 bytes) is defined as a bit field.

 

25. The maximum length of the string in a bit string of contiguous bits is

a) 2 MB

b) 4 MB

c) 2 GB

d) 4 GB

Answer: d

Explanation: Bit string is a string of contiguous bits of maximum 4Gbytes in length.

 

26. The integer word is defined as

a) signed 8-bit data

b) unsigned 16-bit data

c) signed 16-bit data

d) signed 32-bit data

Answer: c

Explanation: The integer word is the signed 16-bit data.

 

27. A 16-bit displacement that references a memory location using any of the addressing modes is

a) Pointer

b) Character

c) BCD

d) Offset

Answer: d

Explanation: Offset is a 16-bit or 32-bit displacement that references a memory location using any of the addressing modes.

 

28. A decimal digit can be represented by

a) unsigned integer

b) signed integer

c) unpacked BCD

d) packed BCD

Answer: c

Explanation: Decimal digits from 0-9 are represented by unpacked bytes.

 

29. The 16-bit registers are available with their extended size of 32 bits, by adding the registers with a prefix of

a) X

b) E

c) 32

d) XX

Answer: b

Explanation: A 32 bit register, known as an extended register, is represented by the register name with a prefix of E.

 

30. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by

a) LSP

b) FSP

c) SP

d) None of the mentioned

Answer: c

Explanation: Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP, SI and DI represent the lower 16-bits.

 

31. Which of the following is a data segment register of 80386?

a) ES

b) FS

c) GS

d) All of the mentioned

Answer: d

Explanation: The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS, ES, FS and GS are the four data segment registers.

 

32. The register width used by the 32-bit addressing modes is

a) 8 bits

b) 16 bits

c) 32 bits

d) all of the mentioned

Answer: d

Explanation: The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.

 

33. The flag that is additional in flag register of 80386, compared to that of 80286 is

a) VM flag

b) RF flag

c) VM and RF flag

d) None of the mentioned

Answer: c

Explanation: The VM and RF flags are added to the 80286 flag register, to derive the flag register of 80386.

 

34. The VM (virtual mode) flag is to be set, only when 80386 is in

a) virtual mode

b) protected mode

c) either virtual or protected mode

d) all of the mentioned

Answer: b

Explanation: If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is to be set only when the 80386 is in protected mode.

 

35. In protected mode of 80386, the VM flag is set by using

a) IRET instruction

b) Task switch operation

c) IRET instruction or task switch operation

d) None of the mentioned

Answer: c

Explanation: The VM flag can be set using the IRET instruction or any task switch operation, only in the protected mode.

 

36. During the instruction cycle of 80386, any debug fault can be ignored if

a) VM flag is set

b) VM flag is cleared

c) RF is cleared

d) RF is set

Answer: d

Explanation: If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.

 

37. The RF is not automatically reset after the execution of

a) IRET

b) POPA

c) IRET and POPF

d) IRET and PUSHF

Answer: c

Explanation: The RF is automatically reset after the execution of every instruction, except for the IRET and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL and INT instructions causing a task switch.

 

38. The segment descriptor register is used to store

a) attributes

b) limit address of segments

c) base address of segments

d) all of the mentioned

Answer: d

Explanation: The segment descriptor register is used to store the descriptor information like attributes, limit and base addresses of segments.

 

39. If the 80386 enters the protected mode from the real address mode, then it returns back to the real mode, by performing the operation of

a) read

b) write

c) terminate

d) reset

Answer: d

Explanation: If the 80386 enters the protected mode from the real address mode, then it cannot return back to the real mode without a reset operation.

 

40. The unit that is needed for virtual mode 80386, only to run the 8086 programs, which require more than 1 Mbyte of memory for memory management functions, is

a) execution unit

b) central processing unit

c) paging unit

d) segmentation unit

Answer: c

Explanation: Paging unit is not necessarily enabled in the virtual mode, but may be needed to run the 8086 programs, which require more than 1 Mbyte of memory, for memory management functions.

 

41. The number of pages that the paging unit allows, in the virtual mode of 80386 is

a) 64

b) 128

c) 256

d) 512

Answer: c

Explanation: In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size. Each of the pages may be located anywhere within the maximum 4Gbytes physical memory.

 

42. The privilege level at which the real mode programs are executed is

a) level 0

b) level 1

c) level 2

d) level 3

Answer: a

Explanation: The real mode programs are executed at the highest privilege level i.e. level 0.

 

43. The instructions to prepare the processor for protected mode can only be executed at the privilege level

a) level 0

b) level 1

c) level 2

d) level 3

Answer: a

Explanation: The instructions to prepare the processor for protected mode can only be executed at the level 0.

 

44. The instruction that is unable to set or read the VM (Virtual Mode) bit is

a) PUSHF

b) IRET

c) POPF

d) PUSHF and POPF

Answer: d

Explanation: The PUSHF and POPF instructions are unable to set or read the VM (Virtual Mode) bit, as they do not access it. The virtual mode can be entered by using IRET instruction.

 

45. If the CKM pin of 80387 is high, then 80387 is operated in

a) real address mode

b) protected mode

c) synchronous mode

d) asynchronous mode

Answer: c

Explanation: If the CKM pin of 80387 is high, then 80387 is operated in synchronous mode. If it is low, then 80387 is operated in asynchronous mode.

 

46. The unit that handles the data and directs it to either FIFO or instruction decoder depending on the bus control logic directive is

a) paging unit

b) central processing unit

c) segmentation unit

d) data interface and control unit

Answer: d

Explanation: The data interface and control unit handles the data, and direct it to either FIFO or instruction decoder, depending on the bus control logic directive.

 

47. The unit that is responsible for carrying out all the floating point calculations, allotted to the coprocessor by 80386, is

a) Central processing unit

b) ALU

c) FPU

d) None of the mentioned

Answer: c

Explanation: The FPU (floating point unit) is responsible for carrying out all the floating point calculations, allotted to the coprocessor by 80386.

 

48. The sizes of instruction and data pointer registers of 80387 respectively are

a) 32-bit, 32-bit

b) 48-bit, 32-bit

c) 32-bit, 48-bit

d) 48-bit, 48-bit

Answer: d

Explanation: 80387 consists of two 48-bit registers, known as instruction and data pointer registers.

 

49. To inform 80387 that the CPU wants to communicate with NPS1, the NPS1 line is directly connected to

a) A31

b) A30

c) M/IO

d) D31

Answer: c

Explanation: The NPS1 and NPS2 lines are directly connected with M/IO and A31 respectively, to inform 80387 that the CPU wants to communicate with it (NPS1), and it is using one of the reserved I/O addresses for 80387 (NPS2).

Module 06

1. The address space of the IA-32 is __________

a) 216

b) 232

c) 264

d) 28

Answer: b

Explanation: The number of addressable locations in the memory is called as address space. 

 

2. The addressing method used in IA-32 is ____________

a) Little Endian

b) Big Endian

c) X-Little Endian

d) Both Little and Big Endian

 Answer: a

Explanation: The method of addressing the data in the system. 

 

3. The floating point numbers are stored in general purpose register in IA-32.

a) True

b) False

 Answer: b

Explanation: The floating registers are not stored in general purpose registers as they have a real part and a decimal part. 

 

4. The Floating point registers of IA-32 can operate on operands up to ___________

a) 128 bit

b) 256 bit

c) 80 bit

d) 64 bit

 Answer: d

Explanation: The size of the floating numbers that can be stored in the floating register. 

 

5. The size of the floating registers can be extended upto _________

a) 128 bit

b) 256 bit

c) 80 bit

d) 64 bit

Answer: c

Explanation: None. 

 

6. The IA-32 architecture associates different parts of memory called __________ with different usages.

a) Frames

b) Pages

c) Tables

d) Segments

 Answer: d

Explanation: The memory is divided into parts called as segments.

 

7. The PC is incorporated with the help of general purpose registers.

a) True

b) False

 Answer: b

Explanation: Registers are not used to incorporate PC as in other architectures, but a separate space is allocated to it.   

 

8. IOPL stands for ________

a) Input/Output Privilege level

b) Input Output Process Link

c) Internal Output Process Link

d) Internal Offset Privilege Level

Answer: a

Explanation: This indicates the security between the transfers between the I/O devices and memory. 

 

9. In IA-32 architecture along with the general flags, the other conditional flags provided are ___________

a) IOPL

b) IF

c) TF

d) All of the mentioned

 Answer: d

Explanation: These flags are basically used to check the system for exceptions. 

 

10. The register used to serve as PC is called as ___________

a) Indirection register

b) Instruction pointer

c) R-32

d) None of the mentioned

 Answer: b

Explanation: The PC is used to store the next instruction that is going to be executed. 

 

11. The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction prefix bit.

a) True

b) False

 Answer: a

Explanation: This switching enables a wide range of operations to be performed.  

 

12. The Bit extension of the register is denoted with the help of __________ symbol.

a) $

b) `

c) E

d) ~

Answer: c

Explanation: This is used to extend the size of the register. 

 

13. The instruction, ADD R1, R2, R3 is decoded as ___________

a) R1<-[R1]+[R2]+[R3] 

b) R3<-[R1]+[R2] 

c) R3<-[R1]+[R2]+[R3] 

d) R1<-[R2]+[R3] 

Answer: d

Explanation: None. 

 

14. The instruction JG loop does ______

a) jumps to the memory location loop if the result of the most recent arithmetic op is even

b) jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0

c) jumps to the memory location loop if the test condition is satisfied with the value of loop

d) none of the mentioned

 Answer: b

Explanation: This instruction is used to cause a branch based on the outcome of the arithmetic operation.  

 

15. The LEA mnemonic is used to __________

a) Load the effective address of an instruction

b) Load the values of operands onto an accumulator

c) Declare the values as global constants

d) Store the outcome of the operation at a memory location

Answer: a

Explanation: The effective address is the address of the memory location required for the execution of the instruction.

 

16. ______  have been developed specifically for pipelined systems.

a) Utility software

b) Speed up utilities

c) Optimizing compilers

d) None of the mentioned

Answer: c

Explanation: The compilers which are designed to remove redundant parts of the code are called as optimizing compilers. 

 

17. The pipelining process is also called as ______

a) Superscalar operation

b) Assembly line operation

c) Von Neumann cycle

d) None of the mentioned

Answer: b

Explanation: It is called so because it performs its operation at the assembly level.

 

18. The fetch and execution cycles are interleaved with the help of ________

a) Modification in processor architecture

b) Clock

c) Special unit

d) Control unit

Answer: b

Explanation: The time cycle of the clock is adjusted to perform the interleaving.

 

19. Each stage in pipelining should be completed within ___________ cycle.

a) 1

b) 2

c) 3

d) 4

Answer: a

Explanation: The stages in the pipelining should get completed within one cycle to increase the speed of performance.

 

20. In pipelining the task which requires the least time is performed first.

a) True

b) False

Answer: b

Explanation: This is done to avoid starvation of the longer task.

 

21. If a unit completes its task before the allotted time period, then _______

a) It’ll perform some other task in the remaining time

b) Its time gets reallocated to a different task

c) It’ll remain idle for the remaining time

d) None of the mentioned

Answer: c

Explanation: None.

 

22. To increase the speed of memory access in pipelining, we make use of _______

a) Special memory locations

b) Special purpose registers

c) Cache

d) Buffers

Answer: c

Explanation: By using the cache we can reduce the speed of memory access by a factor of 10.

 

23. The periods of time when the unit is idle is called as _____

a) Stalls

b) Bubbles

c) Hazards

d) Both Stalls and Bubbles

Answer: d

Explanation: The stalls are a type of hazards that affect a pipelined system.

 

24. The contention for the usage of a hardware device is called ______

a) Structural hazard

b) Stalk

c) Deadlock

d) None of the mentioned

Answer: a

Explanation: None.

 

25. The situation wherein the data of operands are not available is called ______

a) Data hazard

b) Stock

c) Deadlock

d) Structural hazard

Answer: a

Explanation: Data hazards are generally caused when the data is not ready on the destination side.

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