## [MCQ’s] DLCOA

Exit Intent

#### Computer Fundamentals

1. Any signed negative binary number is recognised by its ________
a) MSB
b) LSB
c) Byte
d) Nibble
Explanation: Any negative number is recognized by its MSB (Most Significant Bit).
If it’s 1, then ít’s negative, else if it’s 0, then positive.

2. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble
Explanation: It can be represented up to 16 different values with the help of a Word. Nibble is a combination of four bits and Byte is a combination of 8 bits. It is “word” that is said to be a collection of 16-bits on most of the systems.

3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the number continuously by 2.
a) Dividing
b) Multiplying
d) Subtracting
Explanation: On multiplying the decimal number continuously by 2, the binary equivalent is obtained by the collection of the integer part. However, if it’s an integer, then it’s binary equivalent is determined by dividing the number by 2 and collecting the remainders.

4. The representation of octal number (532.2)8 in decimal is ________
a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10

5. The decimal equivalent of the binary number (1011.011)2 is ________
a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along with the value at that index position.
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10

6. An important drawback of binary system is ________
a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
Explanation: The most vital drawback of binary system is that it requires very large string of 1’s and 0’s to represent a decimal number. Hence, Hexadecimal systems are used by processors for calculation purposes as it compresses the long binary strings into small parts.

7. The decimal equivalent of the octal number (645)8 is ______
a) (450)10
b) (451)10
c) (421)10
d) (501)10
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
The decimal equivalent of the octal number (645)8 is 6 * 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 * 8 + 5 = 384 + 32 + 5 = (421)10.

8. The largest two digit hexadecimal number is ________
a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
Explanation: (FE)16 is 254 in decimal system, while (FD)16 is 253. (EF)16 is 239 in decimal system. And, (FF)16 is 255. Thus, The largest two-digit hexadecimal number is (FF)16.

9. Representation of hexadecimal number (6DE)H in decimal:
a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base index along with the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.

10. The quantity of double word is ________
a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
Explanation: One word means 16 bits, Thus, the quantity of double word is 32 bits.
Sanfoundry Global Education & Learning Series – Digital Circuits.

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11. 1’s complement of 1011101 is ____________
a) 0101110
b) 1001101
c) 0100010
d) 1100101
Explanation: 1’s complement of a binary number is obtained by reversing the binary bits. All the 1’s to 0’s and 0’s to 1’s.

12. 2’s complement of 11001011 is ____________
a) 01010111
b) 11010100
c) 00110101
d) 11100010
Explanation: 2’s complement of a binary number is obtained by finding the 1’s complement of the number and then adding 1 to it.
2’s complement of 11001011 = 00110100 + 1 = 00110101.

13. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________
a) 01001
b) 11010
c) 10101
d) 10100
Explanation: Steps For Subtraction using 1’s complement are:
-> 1’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and 1 is added to the last bit of the result.
-> Else, if there is no carry, then 1’s complement of the result is found out and a ‘-’ sign preceeds the result.

14. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ____________
a) 0111001
b) 1100101
c) 0110110
d) 1000011
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.

15. On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________
a) 1101100
b) 011101
c) 11010101
d) 11010111
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.

16. On addition of 28 and 18 using 2’s complement, we get ____________
a) 00101110
b) 0101110
c) 00101111
d) 1001111
Explanation: Steps for Binary Addition Using 2’s complement:
-> The binary equivalent of the two numbers are obtained and added using the rules of binary addition.

17. On addition of +38 and -20 using 2’s complement, we get ____________
a) 11110001
b) 100001110
c) 010010
d) 110101011
Explanation: Steps for Binary Addition Using 2’s complement:
-> The 2’s complement of the addend is found out and added to the first number.
-> The result is the 2’s complement of the sum obtained.

18. On addition of -46 and +28 using 2’s complement, we get ____________
a) -10010
b) -00101
c) 01011
d) 0100101
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is 28 and Subtrahend is -46.

19. On addition of -33 and -40 using 2’s complement, we get ____________
a) 1001110
b) -110101
c) 0110001
d) -1001001
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is -40 and Subtrahend is -33.

20. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.

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21. 1’s complement of 1011101 is ____________
a) 0101110
b) 1001101
c) 0100010
d) 1100101
Explanation: 1’s complement of a binary number is obtained by reversing the binary bits. All the 1’s to 0’s and 0’s to 1’s.

22. 2’s complement of 11001011 is ____________
a) 01010111
b) 11010100
c) 00110101
d) 11100010
Explanation: 2’s complement of a binary number is obtained by finding the 1’s complement of the number and then adding 1 to it.
2’s complement of 11001011 = 00110100 + 1 = 00110101.

23. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________
a) 01001
b) 11010
c) 10101
d) 10100
Explanation: Steps For Subtraction using 1’s complement are:
-> 1’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and 1 is added to the last bit of the result.
-> Else, if there is no carry, then 1’s complement of the result is found out and a ‘-’ sign preceeds the result.

24. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ____________
a) 0111001
b) 1100101
c) 0110110
d) 1000011
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.

25. On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________
a) 1101100
b) 011101
c) 11010101
d) 11010111
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.

26. On addition of 28 and 18 using 2’s complement, we get ____________
a) 00101110
b) 0101110
c) 00101111
d) 1001111
Explanation: Steps for Binary Addition Using 2’s complement:
-> The binary equivalent of the two numbers are obtained and added using the rules of binary addition.

27. On addition of +38 and -20 using 2’s complement, we get ____________
a) 11110001
b) 100001110
c) 010010
d) 110101011
Explanation: Steps for Binary Addition Using 2’s complement:
-> The 2’s complement of the addend is found out and added to the first number.
-> The result is the 2’s complement of the sum obtained.

28. On addition of -46 and +28 using 2’s complement, we get ____________
a) -10010
b) -00101
c) 01011
d) 0100101
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is 28 and Subtrahend is -46.

29. On addition of -33 and -40 using 2’s complement, we get ____________
a) 1001110
b) -110101
c) 0110001
d) -1001001
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is -40 and Subtrahend is -33.

30. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.

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31. Which of the following is not a positional number system?
a) Roman Number System
b) Octal Number System
c) Binary Number System
Explanation: The Roman number system isn’t a positional number system since it uses symbols to represent numbers.
The octal number system uses digits from 0-7, the binary number system uses digits from 0-1 whereas, the hexadecimal number system uses digits from 0-15.

32. The value of radix in binary number system is _____________
a) 2
b) 8
c) 10
d) 1
Explanation: In a binary number system, the value of base or radix is 2. The binary system uses only two digits for the representation of numbers, therefore its base id has chosen to be 2.

33. The binary equivalent of the decimal number 10 is __________
a) 0010
b) 10
c) 1010
d) 010
Explanation: To get the binary equivalent of any number, we need to divide the number by 2 and obtain the remainders as :We then write the remainders in the reverse order as 1010 .

34. A computer language that is written in binary codes only is _____
a) machine language
b) C
c) C#
d) pascal
Explanation: Machine Language is written in binary codes only. It can be easily understood by the computer and is very difficult for us to understand. A machine language, unlike other languages, requires no translators or interpreters.

35. The octal equivalent of 1100101.001010 is ______
a) 624.12
b) 145.12
c) 154.12
d) 145.21
Explanation: The octal equivalent is obtained by grouping the numbers into three, from right to left before decimal and from right to left after the decimal place.
Here, i.e. 145.12 is the octal equivalent of the number.

36. The input hexadecimal representation of 1110 is _______________
a) 0111
b) E
c) 15
d) 14
Explanation: In hexadecimal number system, 1110 = 15, which is represented by the alphabet E.
Some representations are:
A 10
B 11
C 12
D 13
E 14
F 15.

37. A bit in a computer terminology means either 0 or 1.
a) True
b) False
Explanation: A bit stands for a binary digit. A binary digit can have only two digits i.e. 0 or 1. A binary number consisting of n-bits is called an n-bit number.

38. Convert the binary equivalent 10101 to its decimal equivalent.
a) 21
b) 12
c) 22
d) 31
Explanation: To convert a binary number to its decimal equivalent follow these steps :
24 * 1 + 23 * 0 + 22 *1 + 21 * 0 + 20 * 1 = 21.

39. Which of the following is not a binary number?
a) 1111
b) 101
c) 11E
d) 000
Explanation: A binary number can have only two possible digits, 0 and 1. In the third option, there is an alphabet E present which makes it an invalid binary number. Alphabets are only allowed in the hexadecimal number system.

40. Which of the following is the correct representation of a binary number?
a) (124)2
b) 1110
c) (110)2
d) (000)2
Explanation: The binary numbers should comprise only two digits 0 and 1.
Also, for the base, the value should be 2 and it should be written as a subscript enclosing the entire number. Here, the fourth option gives the correct representation.

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41. What could be the maximum value of a single digit in an octal number system?
a) 8
b) 7
c) 6
d) 5
Explanation: The maximum value in any number system is one less than the value of the base. The base in an octal number system is 8, therefore, the maximum value of the single digit is 7. It takes digits from 0 to 7.

42. In a number system, each position of a digit represents a specific power of the base.
a) True
b) False
Explanation: In a number system, every digit is denoted by a specific power of base. Like in an octal system, consider the number 113, it will be represented as :
82 * 1 + 81 * 1 + 80 *3.

43. The maximum number of bits sufficient to represent an octal number in binary is _______
a) 4
b) 3
c) 7
d) 8
Explanation: The octal number system comprises of only 8 digits. Hence, three bits (23 = 8) are sufficient to represent any octal number in the binary format.

44. The binary number 111 in octal format is ________________
a) 6
b) 7
c) 8
d) 5
Explanation: Certain binary to octal representations are :
000=0
001=1
010=2
011=3
100=4
101=5
110=6
111=7.

45. Convert (22)8 into its corresponding decimal number.
a) 28
b) 18
c) 81
d) 82
Explanation: To convert an octal number to decimal number:
81 * 2 + 80 * 2 = 16 + 2 = 18.
Hence, the decimal equivalent is 18.

46. The octal equivalent of the binary number (0010010100)2 is ______________
a) 422
b) 242
c) 224
d) 226
Explanation: To obtain the octal equivalent, we take numbers in groups of 3, from right to left

47. Octal subtraction of (232)8 from (417)8 will give ______________
a) 165
b) 185
c) 815
d) 516
Explanation: Octal subtraction is done as follows:
417
– 232
________
165
The octal subtraction is the same as that of any other number system. The only difference is, like in a decimal number system, we borrow a group of 10, in a binary system we borrow a group of 2, in an octal number system, we borrow in groups of 8.

48. The 1’s complement of 0.101 is _________________
a) 1.010
b) 0.010
c) 0.101
d) 1.101
Explanation: The 1’s complement of a number is obtained by reversing the bits with value 1 to 0 and the bits with value 0 to 1.
Here, 0.101 gets converted to 1.010 in its 1’s complement format.

a) A01
b) A02
c) B01
d) C01
Explanation: To convert octal to hexadecimal, we first write binary format of the number and then make groups of 4 bits from right to left. Therefore, the hexadecimal equivalent is (B01)16.

50. Express the decimal format of the signed binary number (10010)2 .
a) 2
b) 12
c) -12
d) -2
Explanation: The first bit is the sign bit whereas the rest of the bits are magnitude bits. So the number is: 0010 = 21 * 1 =2
But, the sign bit is 1, Therefore the answer is : (-2)10.

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51. What does the symbol D represent in a hexadecimal number system?
a) 8
b) 16
c) 13
d) 14
Explanation: The symbols A, B, C, D, E and F represent 10, 11, 12, 13, 14 and 15 respectively in a hexadecimal system. This system comprises of 15 numbers in total: digits from 0-9 and symbols from A to F.

52. ABC is a valid hexadecimal number.
a) True
b) False
Explanation: In a hexadecimal number system, alphabets are used for the representation of numbers from 10 to 15. Here, A represents 10, B represents 11 and C represents 12. Therefore, it is a valid hexadecimal number.

53. The maximum number of bits sufficient to represent a hexadecimal number in binary:
a) 4
b) 3
c) 7
d) 8
Explanation: The hexadecimal number system comprises of only 15 symbols: 10 digits and 5 symbols. Hence, three bits (24 = 16) are sufficient to represent any hexadecimal number in the binary format.

54. The binary number 1110 in hexadecimal format is _____________
a) 6
b) E
c) 14
d) 15
Explanation: Certain binary to hexadecimal representations are :
1010=A
1011=B
1100=C
1101=D
1110=E
1111=F.

55. Convert (52)16 into its decimal equivalent.
a) 28
b) 83
c) 80
d) 82
Explanation: To convert a hexadecimal number to decimal number:
161 * 5 + 160 * 2 = 80 + 2 = 82
Hence, the decimal equivalent is 82.

56. The hexadecimal equivalent of the binary number (0010010100)2 is :
a) (0B4)16
b) (0A4)16
c) 224
d) 0114
Explanation: To obtain the octal equivalent, we take numbers in groups of 3, from right to left as :

a) 557
b) 185
c) 815
d) 516
Explanation: Octal subtraction is done as follows:
3A5
+ 1B2
________
557
In hexadecimal addition of alphabets, we add the corresponding numbers they represent and then subtract the result from 16, then generate a carry of 1 to the next set of numbers.
Here, 5+2=7
A+B=10+11=21-16=5
3+1+1(carry)=5.

58. The 2’s complement of 10.11 :
a) 10
b) 0.010
c) 01.01
d) 10.01
Explanation: The 1’s complement of a number is obtained by reversing the bits with value 1 to 0 and the bits with value 0 to 1. Here, 10.11 gets converted to 01.00 in its 1’s complement format. Further, to convert 1’s complement into 2’s, we add 1 to the result. Here, 01.00+1=10.00.

a) (A01)16
b) (A02)16
c) (D5A)16
d) (C01)16
Explanation: To convert octal to hexadecimal, we first write binary format of the number and then make groups of 4 bits from right to left. Therefore, the hexadecimal equivalent is (D5A)16.

60. What do we call the point(decimal) in any hexadecimal number of the form 111.A3?
c) decimal
d) octal point
Explanation: The decimal is often referred to as the hexadecimal point in hexadecimal representation of numbers.
It is referred to as the octal point in octal numbers.

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61. A group of bits used to represent a symbol is called a ____________
a) byte
b) memory
c) nibble
d) code
Explanation: In binary coding, every symbol that appears in data is represented by a group of bits, which are called bytes. Computer codes use binary coding schemes.

62. BCD uses 6 bits to represent a symbol.
a) True
b) False
Explanation: In a Binary Coded Decimal format, 64 characters i.e. 26 different characters can be represented. It is one of the early computer codes.

63. Which of the following is not a type of computer code?
a) EBCDIC
b) BCD
c) ASCII
d) EDIC
Explanation: There is no coding scheme like EDIC. EBCDIC stands for Extended Binary Coded Decimal Interchange Code. BCD stands for Binary Coded Decimal. ASCII stands for American Standard Code for information interchange.

64. The BCD representation of (34)10 is _______________
a) 6
b) 7
c) 8
d) 5
Explanation: BCD numbers are represented as:
34 = (0011 0100)BCD.
Each digit is individually taken and an equivalent standard 4 bit term is written for the respective digit.

65. Perform BCD addition of (23)BCD + (20)BCD .
a) 00110100
b) 01000011
c) 10011
d) 11100
Explanation: To add any two BCD numbers :
Simply perform the addition : 23+20=43.
Then, write the equivalent BCD number = (0100 0011)BCD.

66. The weights used in Binary coded decimal code are:
a) 4,2,1
b) 8,4,2,1
c) 6,4,2,1
d) 2,1
Explanation: BCD is a weighted code and it uses the weights 8,4,2,1 respectively. It is often called the 8421 code. Since, it uses 4 bits for the representation therefore the weights are assigned as : 23 = 8, 22 = 4, 21 = 2, 20 = 1.

67. Write the decimal equivalent for (110001)BCD.
a) 31
b) 13
c) C1
d) 1C
Explanation: To obtain the decimal equivalent :
We start from the rightmost bit and make groups of 4, then write the decimal equivalent accordingly.
0011 0001 = (31)10.

68. The 9’s complement of 45 is _____________
a) 45
b) 54
c) 64
d) 46
Explanation: The 9’s complement of a number is obtained by subtracting each digit from 9. Here, 99-45=54. Therefore, the 9’s complement is 54.

69. The 10’s complement of 455 is _________
a) 543
b) 544
c) 545
d) 546
Explanation: To obtain the 10’s complement, we first obtain the 9’s complement and then add 1 to it.
999-455=544 (9’s)
544+1=545(10’s).

70. The Excess-3 representation of (0100)BCD is __________
a) 0110
b) 1110
c) 0111
d) 1100
Explanation: The excess-3 code is obtained by adding 3 to the BCD code.
Here, 0100+0011=0111.
Also, 4+3=7.

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71. What does ASCII stand for?
a) American Standard Code for Information Interchange
b) American Scientific Code for Information Interchange
c) American Scientific Code for Interchanging Information
d) American Standard Code for Interchanging Information
Explanation: The ASCII codes are used to represent the bits into symbols and vice versa. ASCII is the American Standard Code which is used to exchange information.

72. The decimal representation for the character ‘!’ in ASCII is ____________
a) 31
b) 32
c) 33
d) 34
Explanation: The decimal representation of a few basic characters are:
33 : !
34 : ”
35: #
36 :\$.

73. The two types of ASCII are _____________ and ____________
a) ASCII-4 and ASCII-8
b) ASCII-8 and ASCII-16
c) ASCII-7 and ASCII-8
d) ASCII-4 and ASCII-16
Explanation: The two types of ASCII are ASCII-7 and ASCII-8. ASCII-7 uses 7 bits for the representation of numbers and ASCII-8 uses 8-bits.

74. Any set of digits or alphabets are generally referred as ______________
a) Characters
b) Symbols
c) Bits
d) Bytes
Explanation: We refer to the digits and alphabets generally as characters. A character is generally a unit of information in computers.

75. The first 128 characters are the same in both the types of ASCII i.e. ASCII-7 and ASCII-8.
a) True
b) False
Explanation: There are two types of ASCII codes: ASCII-7 and ASCII-8. ASCII-7 uses 7 bits to represent a number whereas ASCII-8 uses 8-bits to represent a number.

76. The number of characters that can be represented in ASCII-8 are ______________
a) 128
b) 256
c) 32
d) 64
Explanation: ASCII-8 can represent 256 different characters. ASCII-8 uses 8-bits for the representation of numbers i.e. it can represent 28 = 256 different characters.

77. The zone of alphabetic characters from A to O in ASCII is _____________
a) 1000
b) 0100
c) 0010
d) 0001
Explanation: The zone used by ASCII for alphabets is 0100. For e.g. A is represented as 0100(zone)0001(digit). The hex equivalent is 41 for A. The zone used by numbers is 0011.

78. The representation of the number 8 in binary in ASCII-8 format _________
a) 00111000
b) 01001000
c) 1000
d) 00011000
Explanation: The ASCII-8 format will have 8 bits. The zone for the character 8 is 0011 and the digit is 1000. Therefore, its representation is 00111000.

79. Binary Coding for the letter X is ______________
a) 01011000
b) 00111000
c) 10001000
d) 00010100
Explanation: The binary coding for the letter X is 01011000. Here, 0101 is the zone whereas 1000 is the digit. The alphabets from P to Z have the zone 0101.

80. Express the ASCII equivalent of the signed binary number (00110010)2.
a) 2
b) 1
c) A
d) ,
Explanation: The ASCII characters for the remaining options are:
1 : 00110001
A : 01000001
, : 00101100.

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81. The code where all successive numbers differ from their preceding number by single bit is __________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Explanation: The code where all successive numbers differ from their preceding number by single bit is gray code. It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next. BCD Code is one in which decimal digits are represented by a group of 4-bits each, whereas, in Excess-3 Code, the decimal numbers are incremented by 3 and then written in their BCD format.

82. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

83. How many AND gates are required to realize Y = CD + EF + G?
a) 4
b) 5
c) 3
d) 2
Explanation: To realize Y = CD + EF + G, two AND gates are required and two OR gates are required.

84. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
Explanation: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be 00.

85. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.

86. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
Explanation: An Universal Logic Gate is one which can generate any logic function and also the three basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic function and are thus Universal Logic Gates.

87. A full adder logic circuit will have __________
a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there. In case of half adder circuit, there are only two inputs bits and two outputs (SUM and CARRY).

88. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
Explanation: There are three product terms. So, three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.

89. Which of the following are known as universal gates?
a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates, and also they can generate the 3 basic gates AND, OR and NOT.

90. The gates required to build a half adder are __________
a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
Explanation: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the SUM of the two input bits whereas AND outputs the CARRY of the two input bits.

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91. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
Explanation: A transistor can be used as a switch. That is when base is low collector is high (input zero, output one) and base is high collector is low (input 1, output 0).

92. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16
Explanation: For 4 inputs: 24 = 16 truth table entries are necessary.

93. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH
b) At least one input is LOW
c) All inputs are HIGH
d) All inputs are LOW
Explanation: For AND gate, the output is high only when both inputs are high. That’s why the high output in AND will occurs only when all the inputs are high. However, in case of OR gate, if atleast one input is high, the output will be high.

94. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates
Explanation: Expression for XOR is: A.(B’)+(A’).B
So in the above expression, the following logic gates are used: AND, OR, NOT.
Thus, 2 AND gates with two-inputs and 1 OR gate with two-inputs will be required for constructing a XOR gate.

95. The basic logic gate whose output is the complement of the input is the ___________
a) OR gate
b) AND gate
c) INVERTER gate
d) XOR gate
Explanation: It is also called NOT gate and it simply inverts the input, such that 1 becomes 0 and 0 becomes 1.

96. The AND function can be used to ___________ and the OR function can be used to _____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
Explanation: The AND gate and OR gate are used for enabling and disabling respectively because of their multiplicity and additivity property. The AND gate outputs 1 when all inputs are at logic 1, whereas the OR gate outputs 0 when all inputs are at logic 0.

97. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR
Explanation: The dependency notation “>=1” inside a block stands for OR operation.

98. If we use an AND gate to inhibit a signal from passing one of the inputs must be ___________
a) LOW
b) HIGH
c) Inverted
d) Floating
Explanation: AND gate means A*B and OR gate means A+B and to inhibit means to get low signal, one of the input must be low. It means (0*1=0 or 1*0=0) we will get low output signal. Thus, AND gate outputs 1 only when all inputs are at logic level 1 else it outputs 0.

99. Logic gate circuits contain predictable gate functions that open theirs ____________
a) Outputs
b) Inputs
c) Pre-state
d) Impedance state
Explanation: Logic gate circuits contain predictable gate functions that open their inputs because we are free to give any types of inputs.

100. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8
Explanation: 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for +vcc and remaining pins used for connections. For a NAND gate two inputs are required and one output is obtained means for NAND gate 3 pin connections are required. Thus, a 7400IC contains 4 NAND gates with each having 3 pins. Therefore, total 12 pins dedicated for the NAND operation. Rest 2 pins for power supply.

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101. The ______ format is usually used to store data.
a) BCD
b) Decimal
d) Octal
Explanation: The data usually used by computers have to be stored and represented in a particular format for ease of use.

102. The 8-bit encoding format used to store data in a computer is ______
a) ASCII
b) EBCDIC
c) ANCI
d) USCII
Explanation: The data to be stored in the computers have to be encoded in a particular way so as to provide secure processing of the data.

103. A source program is usually in _______
a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
Explanation: The program written and before being compiled or assembled is called as a source program.

104. Which memory device is generally made of semiconductors?
a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
Explanation: Memory devices are usually made of semiconductors for faster manipulation of the contents.

105. The small extremely fast, RAM’s are called as _______
a) Cache
b) Heaps
c) Accumulators
d) Stacks
Explanation: These small and fast memory devices are compared to RAM because they optimize the performance of the system and they only keep files which are required by the current process in them

106. The ALU makes use of _______ to store the intermediate results.
a) Accumulators
b) Registers
c) Heap
d) Stack
Explanation: The ALU is the computational center of the CPU. It performs all mathematical and logical operations. In order to perform better, it uses some internal memory spaces to store immediate results.

107. The control unit controls other units by generating ___________
a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
Explanation: This unit is used to control and coordinate between the various parts and components of the CPU.

108. ______ are numbers and encoded characters, generally used as operands.
a) Input
b) Data
c) Information
d) Stored Values
Explanation: None.

109. The Input devices can send information to the processor.
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases
Explanation: The input devices use buffers to store the data received and when the buffer has some data it sends it to the processor.

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110. ______ bus structure is usually used to connect I/O devices.
a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
Explanation: BUS is a bunch of wires which carry address, control signals and data. It is used to connect various components of the computer.

111. The I/O interface required to connect the I/O device to the bus consists of ______
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
Explanation: The I/O devices are connected to the CPU via BUS and to interact with the BUS they have an interface.

112. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
Explanation: The time required to access a part of the memory for data retrieval.

113. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
Explanation: Virtual memory is like an extension to the existing memory.

114. MFC stands for ___________
a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command
Explanation: This is a system command enabled when a memory function is completed by a process.

115. The time delay between two successive initiations of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
Explanation: The time is taken to finish one task and to start another.

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#### Data Representation and Arithmetic Algorithm

Module 2
1.Perform binary addition of 1101 + 0010 is ________
a) 1110
b) 1111
c) 0111
d) 1,1101
Explanation: The addition is performed as :
1101
+ 0010
_______
1111
Therefore, the result is 1111.

2.The addition 1+1 gives 0 as a result.
a) True
b) False
Explanation: The two result obtained is 0 with a carry of 1. This carry is transferred to the next higher column.

3. The result of 0*1 in binary is ____________
a) 0
b) 1
c) invalid
d) 10
Explanation: The binary multiplication of any number with 0 will give the result 0 itself. Any binary number when multiplied by 0 gives 0 only. e.g. 1101 * 0000 = 0000.

4.The multiplication of 110 * 111 is performed. What is a general term used for 111?
a) Dividend
b) Quotient
c) Multiplicand
d) Multiplier
Explanation: 111 is called the multiplier.
Whenever a multiplication is performed the second term is called the multiplier whereas the first term is called the multiplicand.

5.The result obtained on binary multiplication of 1010 * 1100 is _____________
a) 0001111
b) 0011111
c) 1111100
d) 1111000
Explanation: The solution is as follows :
1010
*  1100
________

0000
0000
1010
1010
_______
1111000

6. Which of the following is often called the double precision format?
a) 64-bit
b) 8-bit
c) 32-bit
d) 128-bit
Explanation: The 64-bit format is referred to as the double precision format. It has 1 sign bit, 8 exponent bits and 23 bits for the mantissa.

7.What do you call the intermediate terms in binary multiplication?
a) Multipliers
b) Mid terms
c) Partial Products
d) Multiplicands
Explanation: The intermediate terms are called partial terms. The mid terms obtained in the binary multiplications are the partial ones whereas the answer obtained is called the final product.

8.The result that is smaller than the smallest number obtained is referred to as ___________
a) NaN
b) Underflow
c) Smallest
d) Mantissa
Explanation: It is referred to as underflow. Nan stands for not a number. Mantissa is the part after the decimal.

9.The number of sign bits in a 32-bit IEEE format is _______
a) 1
b) 11
c) 9
d) 23
Explanation: There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.

10.Express the decimal format of the signed binary number (101010)2 .
a) 10
b) 12
c) -12
d) -10
Explanation: The first bit is the sign bit whereas the rest of the bits are magnitude bits. So the number is: 01010 =23 * 1 + 21 * 1 =8+2 =10.
But , the sign bit is 1,
Therefore the answer is : (-2)10.

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11.__________________ is a straightforward method of representing positive and negative numbers.
b) Complement
c) Sign Magnitude
d) Encode
Explanation: Sign Magnitude is used for the representation of positive and negative numbers. If the leftmost digit is 0, the number is positive. If the leftmost digit is 1, the number is negative.

12.The additive inverse of a number is the number which when added to the original number gives 1 as a result.
a) True
b) False
Explanation: Additive Inverse of a number is the number which gives 0 and not 1 when added to the original number. e.g. number=45, additive inverse =-45, after addition they give 0.

13.The 1’s complement of 1 in 4 bits is __________
a) 0001
b) 0
c) 1001
d) 1110
Explanation: 1’s complement is obtained by reversing the bits from 0 to 1 and vice-versa. Binary of 1 is : 0001 and 1’s complement is : 1110.

14.The binary number 111 in its 2’s complement form is ____________
a) 010
b) 001
c) 000
d) 111
Explanation: 2’s complement is obtained by adding 1 to the 1’s complement. 1’s complement of 111: 000 and 2’s complement:001.

15. The sign magnitude representation of -9 is ___________
a) 00001001
b) 11111001
c) 10001001
d) 11001
Explanation: In case of a negative number, the leftmost digit is 1 if the number is negative. Therefore, +9=00001001 and -9=10001001. Similarly for all other negative numbers.

16.If you are given a word of size n bits, the range of 2’s complement of binary numbers is ________
a) -2n+1 to +2n+1
b) -2n-1 to +2n-1
c) -2n-1 to +2n+1
d) -2n-1 to +2n-1-1
Explanation: 2’s complement is obtained by adding 1 to the 1’s complement. For e.g. 5 :0101 and 1’s complement=1010 and 2’s complement=1011.

17.In both signed magnitude and 2’s complement , positive and negative numbers are separated using ______________
a) LSB
b) MSB
c) 0
d) 1
Explanation: The positive and negative numbers are separated using the MSB. MSB is the Most Significant Bit. MSB is the leftmost bit. e.g. If 1000 is the number then 1 is the most significant bit.

18.Single Precision format comprises of _________ bits.
a) 4
b) 8
c) 16
d) 32
Explanation: The single precision format comprises of 32-bits. It has 1 sign bit, 8 bits for exponent and 23 for the mantissa.

19.If m is the 2’s complement and n is the binary number, then ______________
a) m=n’
b) m=n’+1
c) m=n’-1
d) m=n
Explanation: 2’s complement is simply obtained by addition of 1. So if n is the number and we take the 2’s complement, add 1 to it, we get the 2’s complement. Therefore, m=n’+1.

20.The possible number of bit patterns with 8 bits ________________
a) 128
b) 8
c) 24
d) 256
Explanation: The total number of patterns that can be formed using n-bits are 2n. Here, possible patterns are: 28=256.

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21.Which of the following is used for binary multiplication?
a) Restoring Multiplication
b) Booth’s Algorithm
c) Pascal’s Rule
d) Digit-by-digit multiplication
Explanation: The Booth’s Algorithm is used for the multiplication of binary numbers. It is basically used for the multiplication of 2 signed numbers. This is a very important algorithm in binary arithmetic.

22.One extra bit is added on the left of a binary number, in case of Binary Multiplication using Booth’s Algorithm.
a) True
b) False
Explanation: The statement is true as an extra bit is added when we multiply 2 binary numbers by using Booth’s.
Let us take an example if we multiply 2 * – 3.
The first step is to obtain the binary equivalents.
Hence, 2=10 and -3=01.
Now after adding the extra bit 2=010 and -3=101.
We add 0 in case of positive numbers whereas 1 in negative numbers.

23.The binary number obtained after applying RSC on 11010 will be ___________
a) 11101
b) 10100
c) 01101
d) 01000
Explanation: RSC stands for Right-Shift Circulant. So, whenever the numbers are shifted to the right an extra 0 bit is added to the left. Here, after the right shift of 11010, the number obtained will be 01101.

24.The result of >> of 11001 by 3-bits will be ______________
a) 01000
b) 01111
c) 00011
d) 11111
Explanation: >> is the bitwise left shift operator in binary arithmetic.
Applying >>(left-shift) by 3-bits on the number 11001 will result in 3 zeroes on the right, i.e., 01000.

25.Booth’s Algorithm is applied on _____________
a) decimal numbers
b) binary numbers
d) octal Numbers
Explanation: Booth’s Algorithm is applied only on signed and unsigned binary numbers.
Although, the values of other number systems can be converted to binary, and then the multiplication could be performed.

26.If Booth’s Multiplication is performed on the numbers 22*3, then what is 3 referred to as __________
a) accumulator
b) multiplicand
c) quotient
d) multiplier
Explanation: It is referred to as the multiplier. Multiplier is denoted by Q in booth’s algorithm. 22 is called the multiplicand. These numbers are first converted to their binary equivalents and further the multiplication is performed.

27.What is the default value of accumulator in booth’s multiplication of two 4-bit binary numbers?
a) 0
b) 1
c) 0000
d) 00000
Explanation: The correct answer is d because in case of Booth’s algorithm an extra bit is always added to the binary numbers. The 4-bit binary numbers become 5-bit numbers after adding the extra bit. Accumulator is always assigned 0 bits of the order of the binary numbers whose multiplication is to be performed.

28.What is the value of n in multiplication of 110* 1000?
a) 2
b) 3
c) 4
d) 0
Explanation: In Booth’s, n denotes the number of bits that the higher binary number has when multiplication is performed. Here, since there are 4 bits in 1000, the answer is n=4.

29.What will be the value obtained after multiplication of (-2) * (-3) using Booth’s Algorithm?
a) 6
b) -6
c) -2
d) -3
Explanation: After applying the procedure of Booth’s Algorithm, the value obtained will be 6. Even though the result is obtained in its 2’s complement for but then it is reconverted to its normalized form. Also, the value obtained after decimal multiplication is the same as the value obtained after binary multiplication.

30.What does the data transfer instruction STA stand for?
a) Store Accumulator
b) Send Accumulator
c) Send Action
d) Store Action
Explanation: STA is a data transfer instruction given whenever a value is to be copied on the accumulator. It is used for the fetch operation.

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31.What is the 1’s complement of 11010?
a) 11010
b) 11011
c) 00110
d) 00101
Explanation: The 1’s complement of a number is obtained by converting all the 0 bits to 1 and all 1’s to 0’s. Here, 11010 gets converted to 00101.

32.2’s complement is obtained by adding 1 to 1’s complement of a number.
a) True
b) False
Explanation: The statement is true. Let us take an example: Consider the number 110000.
1’s complement of the number is 001111. 2’s complement=001111+1=010000.

33.The 10’s complement of 562 is __________
a) 4
b) 3
c) 7
d) 8
Explanation: 10’s complement is obtained by adding 1 to the 9’s complement of a number.
Here, 9’s complement=999-562=436.
Therefore, 10’s complement=436+1=437.

34.The 9’s complement of 6578 is ___________
a) 1234
b) 3421
c) 3124
d) 3420
Explanation: 9’s complement is obtained by subtracting 9 from each bit of the number.
Here, 9999-6578=3421.
Therefore, the 9’s complement is 3421.

35. >> operator is used to denote _________
a) left shift
b) right shift
c) greater than
d) less than
Explanation: >> operator denotes the right shift in binary arithmetic.
E.g. If we say, >>110 by 2-bits, the value obtained will be 001.
Similarly, << denotes the right shift operator.

36.The subtraction using 1’s complement of 110 – 100 will give the result ___________
a) -011
b) 011
c) 010
d) -010
Explanation: To subtract using 1’s complement: Take the 1’s complement of the 2nd number (here, 011) and add it to the first number. (110+011=1,001).
If the carry is generated, it is added to the result (001+1=010).
If a carry is not generated then it is converted to its 1’s complement form.

37.The result obtained on subtraction using 2’s complement of 1111-0010 will be _________
a) 11101
b) 11011
c) 1101
d) 1011
Explanation: Firstly, the 2’s complement of the 2nd number is obtained.
Then, if carry is generated, it is discarded and the number is positive.
Otherwise, 2’s complement of the result is obtained and the answer is negative.
Here, 1111+1110=1, 1101. Since carry is generated, it is discarded and the answer is positive.

38.The 1’s complement of 1111111110.101 is _______________
a) 1.010
b) 0000000000.010
c) 1111111110.101
d) 1.101
Explanation: The 1’s complement of a number is obtained by reversing the bits with value 1 to 0 and the bits with value 0 to 1. Here, 11111111110.101 gets converted to 000000001.010 in its 1’s complement format.

39.7’s complement of 432 is _________________
a) 432
b) 543
c) 345
d) 777
Explanation: To find the 7’s complement of any number, we simply subtract 7 from each of the bits.
Here, 777-432=345. So, the 7’s complement is 345.

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40.The 16’s complement of 74E will be __________
a) 8B2
b) F8B2
c) 2B8
d) 8C2
Explanation: The 16’s complement is obtained by subtracting 16 from each of the bits of that number.
Here, 16’s complement of 074E will be F8B2.

41. Binary addition of 1 + 1 gives the result _____________
a) 0
b) 1
c) 2
d) 10
Explanation: The result obtained is 0 with a carry of 1. This carry obtained is added to the next higher column. Binary system can have only two numbers 0 and 1.

42.4-bit is a valid IEEE- format.
a) True
b) False
Explanation: The two main IEEE formats are 16-bit and 32-bit. No format of 4-bit exists. Further, 8-bit format also exists.
In IEEE format, there are certain bits allotted to sign, exponent and mantissa.

43.The result of 0 – 1 in binary is ______________
a) 0
b) 1
c) 11
d) 10
Explanation: The binary subtraction 0 – 1 gives the result 1. A borrow of 1 is although generated and is removed from the next higher column.

44.The complement of any number can be given by a general term _______________
a) Bn – 1 – N
b) Bn -1 + N
c) Bn +1 – N
d) Bn +1 + N
Explanation: Complement of a number can be given by the term :
C= Bn – 1 – N.
Here,
B= base
n= number of digits
N= the number.

45.The IEEE standard followed by almost all the computers for floating point arithmetic _____
a) IEEE 260
b) IEEE 488
c) IEEE 754
d) IEEE 610
Explanation: Most computers follow the IEEE 754 bit format for floating point arithmetic. IEEE stands for electrical and electronic engineers. It has all the floating point arithmetic specifications.

46.Which of the following is often called the double precision format?
a) 64-bit
b) 8-bit
c) 32-bit
d) 128-bit
Explanation: The 64-bit format is referred to as the double precision format. It has 1 sign bit, 8 exponent bits and 23 bits for the mantissa.

47.What is NaN in IEEE standards?
a) Not arithmetic
b) Not a negation
c) Not a number
d) Not a Node
Explanation: It stands for not a number in IEEE standards. A NaN is obtained whenever a result id indeterminate like whenever anything is divided by 0.

48.The result that is smaller than the smallest number obtained is referred to as ___________
a) NaN
b) Underflow
c) Smallest
d) Mantissa
Explanation: It is referred to as underflow. Nan stands for not a number. The mantissa is the part after the decimal.

49.The number of sign bits in a 32-bit IEEE format _________
a) 1
b) 11
c) 9
d) 23
Explanation: There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.

50.Express the decimal format of the signed binary number (101010)2 .
a) 10
b) 12
c) -12
d) -10
Explanation: The first bit is the sign bit whereas the rest of the bits are magnitude bits. So the number is: 01010 =23 * 1 + 21 * 1 =8+2 =10.
But, the sign bit is 1 ,
Therefore the answer is : (-2)10.

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#### Processor Organization and Architecture

Module 3

1. In parts of the processor, adders are used to calculate ____________
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned
Explanation: Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used to calculate addresses, table indices, increment and decrement operators, and similar operations.

2.Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1
Explanation: Total number of inputs in a half adder is two. Since, an EXOR gates has 2 inputs and carry is connected with the input of EXOR gates. The output of half-adder is also 2, them being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.

3.In which operation carry is obtained?
a) Subtraction
c) Multiplication
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 – 1 = 1 (borrow 1).

4.If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is given by A AND B.

5.If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the sum is given by A XOR B.

6.Half-adders have a major limitation in that they cannot __________
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.

a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference between them, while both have two outputs SUM and CARRY.

8.If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.

9.If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B) AND C, which is equivalent to (A AND B) OR (B AND C) OR (C AND A).

10.How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2 OR and 2 EXOR.

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11.What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.

12.Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) DeMultiplexer
Explanation: Data Selector is another name of Multiplexer. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.

13.It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of ___________
a) Inputs
b) Outputs
c) Selection lines
d) Enable lines
Explanation: It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of inputs.

14.Which is the major functioning responsibility of the multiplexing combinational circuit?

a) Decoding the binary information
b) Generation of all minterms in an output function with OR-gate
c) Generation of selected path between multiple sources and a single destination
d) Encoding of binary information
Explanation: The major functioning responsibility of the multiplexing combinational circuit is generation of selected path between multiple sources and a single destination because it makes the circuit too flexible. A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines.

15.What is the function of an enable input on a multiplexer chip?
a) To apply Vcc
b) To connect ground
c) To active the entire chip
d) To active one half of the chip
Explanation: Enable input is used to active the chip, when enable is high the chip works (ACTIVE), when enable is low the chip does not work (MEMORY). However, Enable can be Active-High or Active-Low, indicating it is active either when it is connected to VCC or GND respectively.

16.One multiplexer can take the place of ___________
a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines. Since many operational behaviour can be performed by using a multiplexer. Whereas, a combinational circuit is a combination of many logic gates which makes the circuit more complex.

17.A digital multiplexer is a combinational circuit that selects ___________
a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one
c) Many decimal inputs and transmits the selected information
d) Many decimal outputs and accepts the selected information
Explanation: A digital multiplexer is a combinational circuit that selects one digital information from several sources and transmits the selected information on a single output line depending on the status of the select lines. That is why it is also known as a data selector.

18.In a multiplexer, the selection of a particular input line is controlled by ___________
a) Data controller
b) Selected lines
c) Logic gates
d) Both data controller and selected lines
Explanation: The selection of a particular input line is controlled by a set of selected lines in a multiplexer, which helps to select a particular input from several sources.

19.If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a) 2
b) m
c) n
d) 2n
Explanation: If the number of n selected input lines is equal to 2^m then it requires m select lines to select one of m select lines.

20.How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
Explanation: 2n input lines, n control lines and 1 output line available for MUX. Here, 8 input lines mean 23 inputs. So, 3 control lines are possible. Depending on the status of the select lines, the input is selected and fed to the output.

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21.Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For one input, the demultiplexer gives several outputs. That is why, it is called a data distributor.

22.Most demultiplexers facilitate which type of conversion?
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. Demultiplexer converts single input into multiple outputs.

23.In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
c) 4
d) 5
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. Therefore, for 1:4 demultiplexer, 2 select lines are required.

24.In a multiplexer the output depends on its ___________
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As the select input changes, the output of the multiplexer varies according to that input.

25. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this case n = 3 since 23 = 8.

26.How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
Explanation: The number of AND gates required will be equal to the number of outputs in a demultiplexer, which are 8.

27.Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input

28.Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are directly connected to the other’s output. Such types of structure is called cross coupling and due to which latches remain in the latched condition.

29.One example of the use of an S-R flip-flop is as ___________
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused during the switching of electronic devices.

30.The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or Undefined State occurs at both S and R being at 1.

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31.When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set and Toggle.

32.Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Explanation: In D flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid state at both inputs being 1.

33.A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross coupling means the output of second gate is fed to the input of first gate and vice-versa.

34.The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called sequential circuits. Unlike sequential circuits, if output depends only on the present state, then it’s known as combinational circuits.

35.Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Explanation: Combinational circuits are often faster than sequential circuits. Since, the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. Latches and Flip-flops come under sequential circuits.

36.How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock signal.

37.The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
Explanation: The sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information.

38.The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the second output Q’ = 1 and vice versa.

39.In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.

40.The output of latches will remain in set/reset untill ___________
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change the state.

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41.A register is defined as ___________
a) The group of latches for storing one bit of information
b) The group of latches for storing n-bit of information
c) The group of flip-flops suitable for storing one bit of information
d) The group of flip-flops suitable for storing binary information
Explanation: A register is defined as the group of flip-flops suitable for storing binary information. Each flip-flop is a binary cell capable of storing one bit of information. The data in a register can be transferred from one flip-flop to another.

42.The register is a type of ___________
a) Sequential circuit
b) Combinational circuit
c) CPU
d) Latches
Explanation: Register’s output depends on the past and present states of the inputs. The device which follows these properties is termed as a sequential circuit. Whereas, combinational circuits only depend on the present values of inputs.

43.How many types of registers are?
a) 2
b) 3
c) 4
d) 5
Explanation: There are 4 types of shift registers, viz., Serial-In/Serial-Out, Serial-In/Parallel-Out, Parallel-In/Serial-Out and Parallel-In/Parallel-Out.

44.The main difference between a register and a counter is ___________
a) A register has no specific sequence of states
b) A counter has no specific sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) A register counts data
Explanation: The main difference between a register and a counter is that a register has no specific sequence of states except in certain specialised applications.

45.In D register, ‘D’ stands for ___________
a) Delay
b) Decrement
c) Data
d) Decay
Explanation: D stands for “data” in case of flip-flops and not delay. Registers are made of a group of flip-flops.

50.Registers capable of shifting in one direction is ___________
a) Universal shift register
b) Unidirectional shift register
c) Unipolar shift register
d) Unique shift register
Explanation: The register capable of shifting in one direction is unidirectional shift register. The register capable of shifting in both directions is known as a bidirectional shift register.

51.A register that is used to store binary information is called ___________
a) Data register
b) Binary register
c) Shift register
d) D – Register
Explanation: A register that is used to store binary information is called a binary register. A register in which data can be shifted is called shift register.

52.A shift register is defined as ___________
a) The register capable of shifting information to another register
b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only
Explanation: The register capable of shifting information either to the right or to the left is termed as shift register. A register in which data can be shifted only in one direction is called unidirectional shift register, while if data can shifted in both directions, it is known as a bidirectional shift register.

53.How many methods of shifting of data are available?
a) 2
b) 3
c) 4
d) 5
Explanation: There are two types of shifting of data are available and these are serial shifting & parallel shifting.

54.In serial shifting method, data shifting occurs ____________
a) One bit at a time
b) simultaneously
c) Two bit at a time
d) Four bit at a time
Explanation: As the name suggests serial shifting, it means that data shifting will take place one bit at a time for each clock pulse in a serial fashion. While in parallel shifting, shifting will take place with all bits simultaneously for each clock pulse in a parallel fashion.

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#### Control Unit Design

1. ________ are the different type/s of generating control signals.
a) Micro-programmed
b) Hardwired
c) Micro-instruction
d) Both Micro-programmed and Hardwired

Explanation: The above is used to generate control signals in different types of system architectures.

2. The type of control signal is generated based on ________
a) contents of the step counter
b) Contents of IR
c) Contents of condition flags
d) All of the mentioned

Explanation: Based on the information above the type of control signal is decided.

3. What does the hardwired control generator consist of?
a) Decoder/encoder
b) Condition codes
c) Control step counter
d) All of the mentioned

Explanation: The CU uses the above blocks and IR to produce the necessary signal.

4. What does the end instruction do?
a) It ends the generation of a signal
b) It ends the complete generation process
c) It starts a new instruction fetch cycle and resets the counter
d) It is used to shift the control to the processor

Explanation: It is basically used to start the generation of a new signal.

5. The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4.BR…
a) True
b) False

Explanation: The signal is generated using the logic of the formula above.

6. What does the RUN signal do?
a) It causes the termination of a signal
b) It causes a particular signal to perform its operation
c) It causes a particular signal to end
d) It increments the step counter by one

Explanation: The RUN signal increments the step counter by one for each clock cycle.

7. The name hardwired came because the sequence of operations carried out is determined by the wiring.
a) True
b) False

Explanation: In other words hardwired is another name for Hardware Control signal generator.

8. The benefit of using this approach is ________
a) It is cost effective
b) It is highly efficient
c) It is very reliable
d) It increases the speed of operation

9. The disadvantage/s of the hardwired approach is ________
a) It is less flexible
b) It cannot be used for complex instructions
c) It is costly
d) less flexible & cannot be used for complex instructions

Explanation: The more complex the instruction set less applicable to a hardwired approach.

10. The End signal is generated using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…
a) True
b) False

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11. In micro-programmed approach, the signals are generated by ______
a) Machine instructions
b) System programs
c) Utility tools
d) None of the mentioned

Explanation: The machine instructions generate the signals.

12. A word whose individual bits represent a control signal is ______
a) Command word
b) Control word
c) Co-ordination word
d) Generation word

Explanation: The control word is used to get the different types of control signals required.

13. A sequence of control words corresponding to a control sequence is called _______
a) Micro routine
b) Micro function
c) Micro procedure
d) None of the mentioned

Explanation: The micro routines are used to perform a particular task.

14. Individual control words of the micro routine are called as ______
b) Micro operation
c) Micro instruction
d) Micro command

Explanation: The each instruction which put together performs the task.

15. The special memory used to store the micro routines of a computer is ________
a) Control table
b) Control store
c) Control mart
d) Control shop

Explanation: The control store is used as a reference to get the required control routine.
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16. To read the control words sequentially _________ is used.
a) PC
b) IR
c) UPC
d) None of the mentioned

Explanation: The UPC stands for Micro program counter.

17. Every time a new instruction is loaded into IR the output of ________ is loaded into UPC.
d) Clock

18. The case/s where micro-programmed can perform well _______________
a) When it requires to check the condition codes
b) When it has to choose between the two alternatives
c) When it is triggered by an interrupt
d) None of the mentioned

19. The signals are grouped such that mutually exclusive signals are put together.
a) True
b) False

Explanation: This is done to improve the efficiency of the controller.

20. Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is ________
a) Horizontal organisation
b) Vertical organisation
c) Diagonal organisation
d) None of the mentioned

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#### Memory Operation

1. Any electronic holding place where data can be stored and retrieved later whenever required is ____________
a) memory
b) drive
c) disk
d) circuit

Explanation: Memory is the place where data can be stored and later retrieved. Memory can be of classified into register, cache, main memory, etc.

2. Cache memory is the onboard storage.
a) True
b) False

Explanation: Cache Memory is the memory closest to the CPU. Registers, Cache and the main memory are the means of onboard storage in the computer system.

3. Which of the following is the fastest means of memory access for CPU?
a) Registers
b) Cache
c) Main memory
d) Virtual Memory

Explanation: Registers are the fastest means of access for CPU. Registers are the small memory locations which are present closest to the CPU.

4. The memory implemented using the semiconductor chips is _________
a) Cache
b) Main
c) Secondary
d) Registers

Explanation: The main memory is implemented using semiconductor chips. Main memory is located on the motherboard. It mainly consists of RAM and small amount of ROM.

5. Size of the ________ memory mainly depends on the size of the address bus.
a) Main
b) Virtual
c) Secondary
d) Cache

Explanation: The size of the main memory depends on the size of the address bus of the CPU. The main memory mainly consists of RAM and ROM, where RAM contains the current data and programs and ROM contains permanent programs like BIOS.

6. Which of the following is independent of the address bus?
a) Secondary memory
b) Main memory
c) Onboard memory
d) Cache memory

Explanation: The secondary memory is independent of the address bus. It increases the storage space. It is implemented in the form of magnetic storage devices.

7. ____________ storage is a system where a robotic arm will connect or disconnect off-line mass storage media according to the computer operating system demands.
a) Secondary
b) Virtual
c) Tertiary
d) Magnetic

Explanation: The tertiary storage is the correct option. It is used in the realms of enterprise storage and scientific computing on large computer systems and business computer networks and is something a typical personal computer never sees firsthand.

8. What is the location of the internal registers of CPU?
a) Internal
b) On-chip
c) External
d) Motherboard

Explanation: The internal registers are present on-chip. They are therefore present inside the CPU. L1 cache is also present on-chip inside the CPU.

9. MAR stands for ___________
c) Main accessible register
d) Memory accessible register

Explanation: The MAR stands for memory address register. It holds the address of the active memory location.

10. If M denotes the number of memory locations and N denotes the word size, then an expression that denotes the storage capacity is ______________
a) M*N
b) M+N
c) 2M+N
d) 2M-N

Explanation: Storage capacity is the product of a number of memory locations that is the number of words and the word size or the number of bits stored per location. Storage capacity should be as large as possible.

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11. What is the high speed memory between the main memory and the CPU called?
a) Register Memory
b) Cache Memory
c) Storage Memory
d) Virtual Memory

Explanation: It is called the Cache Memory. The cache memory is the high speed memory between the main memory and the CPU.

12. Cache Memory is implemented using the DRAM chips.
a) True
b) False

Explanation: The Cache memory is implemented using the SRAM chips and not the DRAM chips. SRAM stands for Static RAM. It is faster and is expensive.

13. Whenever the data is found in the cache memory it is called as _________
a) HIT
b) MISS
c) FOUND
d) ERROR

Explanation: Whenever the data is found in the cache memory, it is called as Cache HIT. CPU first checks in the cache memory since it is closest to the CPU.

14. LRU stands for ___________
a) Low Rate Usage
b) Least Rate Usage
c) Least Recently Used
d) Low Required Usage

Explanation: LRU stands for Least Recently Used. LRU is a type of replacement policy used by the cache memory.

15. When the data at a location in cache is different from the data located in the main memory, the cache is called _____________
a) Unique
b) Inconsistent
c) Variable
d) Fault

Explanation: The cache is said to be inconsistent. Inconsistency must be avoided as it leads to serious data bugs.

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16. Which of the following is not a write policy to avoid Cache Coherence?
a) Write through
b) Write within
c) Write back
d) Buffered write

Explanation: There is no policy which is called as the write within policy. The other three options are the write policies which are used to avoid cache coherence.

17. Which of the following is an efficient method of cache updating?
a) Snoopy writes
b) Write through
c) Write within
d) Buffered write

Explanation: Snoopy writes is the efficient method for updating the cache. In this case, the cache controller snoops or monitors the operations of other bus masters.

18. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
a) Associative
b) Direct
c) Set Associative
d) Indirect

Explanation: This happens in the associative mapping. In this case, a block of data from the main memory can be mapped anywhere in the cache memory.

19. The number of sign bits in a 32-bit IEEE format is ____
a) 1
b) 11
c) 9
d) 23

Explanation: There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.

20. The transfer between CPU and Cache is ______________
a) Block transfer
b) Word transfer
c) Set transfer
d) Associative transfe

Explanation: The transfer is a word transfer. In the memory subsystem, word is transferred over the memory data bus and it typically has a width of a word or half-word.
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#### Principle of Advance Processor and Buses

Module 6
1.Any condition that causes a processor to stall is called as _________
a) Hazard
b) Page fault
c) System error
d) None of the mentioned
Explanation: An hazard causes a delay in the execution process of the processor.

2.The periods of time when the unit is idle is called as ________
a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
Explanation: The stalls are a type of hazards that affect a pipe-lined system.

3. The contention for the usage of a hardware device is called ______
a) Structural hazard
b) Stalk
d) None of the mentioned
Explanation: The processor contends for the usage of the hardware and might enter into a deadlock state.

4.The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
d) Structural hazard
Explanation: Data hazards are generally caused when the data is not ready on the destination side.

5. The stalling of the processor due to the unavailability of the instructions is called as ___________
a) Control hazard
b) structural hazard
c) Input hazard
d) None of the mentioned
Explanation: The control hazard also called as instruction hazard is usually caused by a cache miss.

6.The time lost due to the branch instruction is often referred to as ____________
a) Latency
b) Delay
c) Branch penalty
d) None of the mentioned
Explanation: This time also retards the performance speed of the processor.

7.The pipeline bubbling is a method used to prevent data hazard and structural hazards.
a) True
b) False
Explanation: The periods of time when the unit is idle is called a Bubble.

8. ____________ method is used in centralized systems to perform out of order execution.
a) Scorecard
b) Score boarding
c) Optimizing
d) Redundancy
Explanation: In a scoreboard, the data dependencies of every instruction are logged. Instructions are released only when the scoreboard determines that there are no conflicts with previously issued and incomplete instructions.

9.The algorithm followed in most of the systems to perform out of order execution is __________
a) Tomasulo algorithm
b) Score carding
d) None of the mentioned
Explanation: The Tomasulo algorithm is a hardware algorithm developed in 1967 by Robert Tomasulo from IBM. It allows sequential instructions that would normally be stalled due to certain dependencies to execute non-sequentially (out-of-order execution).

10.The problem where process concurrency becomes an issue is called as ___________
a) Philosophers problem
b) Bakery problem
c) Bankers problem

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12.The PCI follows a set of standards primarily used in _____ PC’s.
a) Intel
b) Motorola
c) IBM
d) SUN
Explanation: The PCI BUS has a closer resemblance to IBM architecture.

13.The ______ is the BUS used in Macintosh PC’s.
a) NuBUS
b) EISA
c) PCI
d) None of the mentioned
Explanation: The NuBUS is an extension of the processor BUS in Macintosh PC’s.

14. The key feature of the PCI BUS is _________
a) Low cost connectivity
b) Plug and Play capability
c) Expansion of Bandwidth
d) None of the mentioned
Explanation: The PCI BUS was the first to introduce plug and play interface for I/O devices.

15.PCI stands for _______
a) Peripheral Component Interconnect
b) Peripheral Computer Internet
c) Processor Computer Interconnect
d) Processor Cable Interconnect
Explanation: The PCI BUS is used as an extension for the processor BUS.

16.The PCI BUS supports _____ address space/s.
a) I/O
b) Memory
c) Configuration
d) All of the mentioned
Explanation: The PCI BUS is mainly built to provide a wide range of connectivity for devices.

17.______ address space gives the PCI its plug and plays capability.
a) Configuration
b) I/O
c) Memory
d) All of the mentioned
Explanation: The configuration address space is used to store the details of the connected device.

18._____ provides a separate physical connection to the memory.
a) PCI BUS
b) PCI interface
c) PCI bridge
d) Switch circuit
Explanation: The PCI bridge is a circuit that acts as a bridge between the BUS and the memory.

19. When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave.
a) True
b) False
Explanation: The address is stored by the slave in a buffer and hence it is not required by the master to hold it.

20.The master is also called as _____ in PCI terminology.
a) Initiator
b) Commander
c) Chief
d) Starter
Explanation: The Master is also called as an initiator in PCI terminology as it is the one that initiates a data transfer.

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21.Signals whose names end in ____ are asserted in the low voltage state.
a) \$
b) #
c) *
d) !

22.The transfer rate, when the USB is operating in low-speed of operation is _____
a) 5 Mb/s
b) 12 Mb/s
c) 2.5 Mb/s
d) 1.5 Mb/s
Explanation: The USB has two rates of operation the low-speed and the full-speed one.

23.The high speed mode of operation of the USB was introduced by _____
a) ISA
b) USB 3.0
c) USB 2.0
d) ANSI
Explanation: The high-speed mode of operation was introduced with USB 2.0, which enabled the USB to operate at 480 Mb/s.

24.The sampling process in speaker output is a ________ process.
a) Asynchronous
b) Synchronous
c) Isochronous
d) None of the mentioned
Explanation: The isochronous process means each bit of data is separated by a time interval.

25.The USB device follows _______ structure.
a) List
b) Huffman
c) Hash
d) Tree
Explanation: The USB has a tree structure with the root hub at the centre.

26.The I/O devices form the _____ of the tree structure.
a) Leaves
b) Subordinate roots
c) Left subtrees
d) Right subtrees
Explanation: The I/o devices form the leaves of the structure.

27.USB is a parallel mode of transmission of data and this enables for the fast speeds of data transfers.
a) True
b) False
Explanation: The USB does a serial mode of data transfer.

28.In USB the devices can communicate with each other.
a) True
b) False
Explanation: It allows only the host to communicate with the devices and not between themselves.

29.The device can send a message to the host by taking part in _____ for the communication path.
a) Arbitration
b) Polling
c) Prioritizing
d) None of the mentioned
Explanation: None.

30.When the USB is connected to a system, its root hub is connected to the ________
a) PCI BUS
b) SCSI BUS
c) Processor BUS
d) IDE
Explanation: The USB’s root is connected to the processor directly using the BUS.

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31.The devices connected to USB is assigned a ____ address.
a) 9 bit
b) 16 bit
c) 4 bit
d) 7 bit
Explanation: To make it easier for recognition the devices are given 7 bit addresses.

32.The USB address space can be shared by the user’s memory space.
a) True
b) False
Explanation: The USB memory space is not under any address spaces and cannot be accessed.

33.The initial address of a device just connected to the HUB is ________
a) AHFG890
b) 0000000
c) FFFFFFF
d) 0101010
Explanation: By standard, the usual address of a new device is zero.

33.Locations in the device to or from which data transfers can take place is called ________
a) End points
b) Hosts
c) Source
d) None of the mentioned

34.A USB pipe is a ______ channel.
a)Simplex
b) Half-Duplex
c) Full-Duplex
d) Both Simplex and Full-Duplex