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Module 1 (Computer Fundamentals ) 5
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DLDA Introduction 05 minLecture1.1
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Binary and Decimal system 21 minLecture1.2
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Octal Number System 18 minLecture1.3
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Hexadecimal Number System 10 minLecture1.4
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COA Introduction 09 minLecture1.5
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Module 2 (Data Representation and Arithmetic Algorithms) 16
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Floating Point Number Representation in IEEE 754 17 minLecture2.1
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Booth’s Algorithm with Solved Example part 1 15 minLecture2.2
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Booth’s Algorithm with Solved Example part 2 10 minLecture2.3
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Booth’s Algorithm with Solved Example part 3 08 minLecture2.4
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Numerical Data Representation 07 minLecture2.5
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Restoring Division Part 01 18 minLecture2.6
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Restoring Division Part 02 10 minLecture2.7
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Non Restoring Division Part 01 12 minLecture2.8
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Non Restoring Division Part 02 10 minLecture2.9
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RISC Microprocessor 12 minLecture2.10
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BCD Arithmetic 11 minLecture2.11
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How to find 1’s and 2’s Complement 12 minLecture2.12
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Subtraction using 1’s & 2’s Complement 10 minLecture2.13
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Codes 10 minLecture2.14
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Codes Non-Weighted 06 minLecture2.15
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BCD XS-3 and Gray Code 13 minLecture2.16
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Module 3 (Processor Organization and Architecture) 7
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Full Adder 14 minLecture3.1
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Half Adder 11 minLecture3.2
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Full Subtractor 08 minLecture3.3
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Half Subtractor 07 minLecture3.4
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Full Subtractor Using Falf Subtractor 07 minLecture3.5
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Full Adder Using Half Adder 08 minLecture3.6
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Conversion of T to D Flip Flop 05 minLecture3.7
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Module 4 (Control Unit Design) 4
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Hardwired Control Unit 08 minLecture4.1
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Micro programmed control unit 08 minLecture4.2
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Hardwired CU vs Micro-programmed CU 10 minLecture4.3
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Wilke’s Control 10 minLecture4.4
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Module 5 (Memory Organization) 12
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Memory and its characteristics 09 minLecture5.1
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DRAM ( Dynamic RAM ) 07 minLecture5.2
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SRAM (Static RAM) 08 minLecture5.3
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Cache Memory Full Concept with working 07 minLecture5.4
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Memory Hierarchy and Locality of Reference 13 minLecture5.5
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Memory Interleaved 10 minLecture5.6
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Virtual Memory & Paging concept 10 minLecture5.7
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Memory Segmentation 10 minLecture5.8
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Demand Paging 11 minLecture5.9
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Cache Coherence Single & Multi Processor 11 minLecture5.10
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Cache Coherence Strategies 09 minLecture5.11
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MESI Write invalidate snoopy protocol 11 minLecture5.12
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Module 6 (Principles of Advanced Processor and Buses) 14
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Basic Concept of Pipeline 10 minLecture6.1
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Parallel Processing and Applications 13 minLecture6.2
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Flynn’s Classification 10 minLecture6.3
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Amdhal’s law 07 minLecture6.4
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Instruction Level Parallelism (ILP) 08 minLecture6.5
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Superscalar Architecture 10 minLecture6.6
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VLIW 10 minLecture6.7
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Superscalar vs VLIW 05 minLecture6.8
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Out of Order Execution 09 minLecture6.9
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BUS and BUS Arbitration 11 minLecture6.10
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BUS Arbitration-Daisy Chaining 08 minLecture6.11
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BUS Arbitration-Polling Method 07 minLecture6.12
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Instruction Cycles and Interrupt Mechanism 07 minLecture6.13
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BUS Arbitration-Independent Request 04 minLecture6.14
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Notes 1
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COALecture7.1
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