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Course Overview
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Module 1 (Computer Fundamentals )
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Module 2 (Data Representation and Arithmetic Algorithms)
- Floating Point Number Representation in IEEE 754
- Booth’s Algorithm with Solved Example Part #1
- Booth’s Algorithm with Solved Example Part #2
- Booth’s Algorithm with Solved Example Part #3
- Numerical Data Representation
- Restoring Division Part #1
- Restoring Division Part #2
- Non Restoring Division Part #1
- Non Restoring Division Part #2
- RISC Microprocessor
- BCD Arithmetic
- How to find 1’s and 2’s Complement
- Subtraction using 1’s & 2’s Complement
- Codes
- Codes Non-Weighted
- BCD XS-3 and Gray Code
- [Notes] Data Representation and Arithmetic Algorithm With Sums
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Module 3 (Processor Organization and Architecture)
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Module 4 (Control Unit Design)
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Module 5 (Memory Organization)
- Memory and its characteristics
- DRAM ( Dynamic RAM )
- SRAM (Static RAM)
- Cache Memory Full Concept with working
- Memory Hierarchy and Locality of Reference
- Memory Interleaving
- Virtual Memory and Paging concept
- Memory Segmentation
- Demand Paging
- Cache Coherence Single and Multiprocessor
- Cache Coherence Strategies
- MESI Write invalidate snoopy protocol
- [Notes] Memory organization
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Module 6 (Principles of Advanced Processor and Buses)
- Basic Concept of Pipeline
- Parallel Processing and Applications
- Flynn’s Classification
- Amdahl’s law
- Instruction Level Parallelism (ILP)
- Superscalar Architecture
- VLIW
- Superscalar vs VLIW
- Out of Order Execution
- BUS and BUS Arbitration
- BUS Arbitration Daisy Chaining
- BUS Arbitration-Polling Method
- Instruction Cycles and Interrupt Mechanism
- BUS Arbitration-Independent Request
- [Notes] Principles of advanced processor and buses
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PDF Notes
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Viva Questions
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Superscalar vs VLIW