DLCOA (Digital Logic & Computer Organization and Architecture)

DLCOA (Digital Logic & Computer Organization and Architecture)

Digital Logic Design and Analysis is the semester 3 subject of computer engineering in Mumbai University. Course Objectives for the subject Digital Logic Design and Analysis is to introduce the fundamental concepts and methods for design of digital circuits and a pre-requisite for computer organization and architecture, microprocessor systems. To provide the concept of designing Combinational and sequential circuits. To provide basic knowledge of how digital building blocks are described in VHDL. Course Outcomes for the subject Digital Logic Design and Analysis At the end of the course student should be able1. To understand different number systems and their conversions. To analyze and minimize Boolean expressions. To design and analyze combinational circuits. To design and analyze sequential circuits. To understand the basic concepts of VHDL. To study basics of TTL and CMOS Logic families.

Digital Logic is the basis of electronic systems, such as computers and cell phones. Digital Logic is rooted in binary code, a series of zeroes and ones each having an opposite value. This system facilitates the design of electronic circuits that convey information, including logic gates. Digital Logic gate functions include and, or and not. The value system translates input signals into specific output. Digital Logic facilitates computing, robotics and other electronic applications. Digital Logic Design is foundational to the fields of electrical engineering and computer engineering. Digital Logic designers build complex electronic components that use both electrical and computational characteristics. These characteristics may involve power, current, logical function, protocol and user input. Digital Logic Design is used to develop hardware, such as circuit boards and microchip processors. This hardware processes user input, system protocol and other data in computers, navigational systems, cell phones or other high-tech systems.

The prerequisite of this subject is Digital Logic Design and Application. Course Objectives of the subject Computer Organization and Architecture is to have a thorough understanding of the basic structure and operation of a digital computer. To discuss in detail the operation of the arithmetic unit including the algorithms & implementation of fixed-point and floating-point addition, subtraction, multiplication & division.  To study the different ways of communicating with I/O devices and standard I/O interfaces. To study the hierarchical memory system including cache memories and virtual memory. Course Outcomes of the subject Computer Organization and Architecture At the end of the course student should be able to. To describe the basic structure of the computer system. To demonstrate the arithmetic algorithms for solving ALU operations. To describe instruction-level parallelism and hazards in typical processor pipelines. To describe superscalar architectures, multi-core architecture, and their advantages to demonstrate the memory mapping techniques. To Identify various types of buses, interrupts, and I/O operations in a computer system.

In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems. Some definitions of architecture define it as describing the capabilities and programming model of a computer but not a particular implementation. In other definitions computer architecture involves instruction set architecture design, microarchitecture design, logic design, and implementation. Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement representation in efficient way, i.e., less number of additions/subtractions required. It operates on the fact that strings of 0’s in the multiplier require no addition but just shifting and a string of 1’s in the multiplier from bit weight 2^k to weight 2^m can be treated as 2^(k+1 ) to 2^m. As in all multiplication schemes, booth algorithm requires examination of the multiplier bits and shifting of the partial product. Prior to the shifting, the multiplicand may be added to the partial product, subtracted from the partial product, or left unchanged according to following rules: The multiplicand is subtracted from the partial product upon encountering the first least significant 1 in a string of 1’s in the multiplier. The multiplicand is added to the partial product upon encountering the first 0 (provided that there was a previous ‘1’) in a string of 0’s in the multiplier. The partial product does not change when the multiplier bit is identical to the previous multiplier bit.

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