## [MCQ’s]Digital System Design

#### Module 01

1. Any signed negative binary number is recognized by its ________
a) MSB
b) LSB
c) Byte
d) Nibble
Explanation: Any negative number is recognized by its MSB (Most Significant Bit).
If it’s 1, then ít’s negative, else if it’s 0, then positive.

2. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble
Explanation: It can be represented up to 16 different values with the help of a Word. Nibble is a combination of four bits and Byte is a combination of 8 bits. It is “word” which is said to be a collection of 16-bits on most of the systems.

3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the number continuously by 2.
a) Dividing
b) Multiplying
d) Subtracting
Explanation: On multiplying the decimal number continuously by 2, the binary equivalent is obtained by the collection of the integer part. However, if it’s an integer, then it’s binary equivalent is determined by dividing the number by 2 and collecting the remainders.

4. The representation of octal number (532.2)8 in decimal is ________
a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10

5. The decimal equivalent of the binary number (1011.011)2 is ________
a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along with the value at that index position.
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10

6. An important drawback of binary system is ________
a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
Explanation: The most vital drawback of binary system is that it requires very large string of 1’s and 0’s to represent a decimal number. Hence, Hexadecimal systems are used by processors for calculation purposes as it compresses the long binary strings into small parts.

7. The decimal equivalent of the octal number (645)8 is ______
a) (450)10
b) (451)10
c) (421)10
d) (501)10
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
The decimal equivalent of the octal number (645)8 is 6 * 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 * 8 + 5 = 384 + 32 + 5 = (421)10.

8. The largest two-digit hexadecimal number is ________
a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
Explanation: (FE)16 is 254 in decimal system, while (FD)16 is 253. (EF)16 is 239 in decimal system. And, (FF)16 is 255. Thus, The largest two-digit hexadecimal number is (FF)16.

9. Representation of hexadecimal number (6DE)H in decimal:
a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base index along with the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.

10. The quantity of double word is ________
a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
Explanation: One word means 16 bits, Thus, the quantity of double word is 32 bits.

11. The given hexadecimal number (1E.53)16 is equivalent to ____________
a) (35.684)8
b) (36.246)8
c) (34.340)8
d) (35.599)8
Explanation: First, the hexadecimal number is converted to it’s equivalent binary form, by writing the binary equivalent of each digit in form of 4 bits. Then, the binary equivalent bits are grouped in terms of 3 bits and then for each of the 3-bits, the respective digit is written. Thus, the octal equivalent is obtained.
(1E.53)16 = (0001 1110.0101 0011)2
= (00011110.01010011)2
= (011110.010100110)2
= (011 110.010 100 110)2
= (36.246)8

12. The octal number (651.124)8 is equivalent to ______
a) (1A9.2A)16
b) (1B0.10)16
c) (1A8.A3)16
d) (1B0.B0)16
Explanation: First, the octal number is converted to it’s equivalent binary form, by writing the binary equivalent of each digit in form of 3 bits. Then, the binary equivalent bits are grouped in terms of 4 bits and then for each of the 4-bits, the respective digit is written. Thus, the hexadecimal equivalent is obtained.
(651.124)8 = (110 101 001.001 010 100)2
= (110101001.001010100)2
= (0001 1010 1001.0010 1010)2
= (1A9.2A)16

13. The octal equivalent of the decimal number (417)10 is _____
a) (641)8
b) (619)8
c) (640)8
d) (598)8
Explanation: Octal equivalent of decimal number is obtained by dividing the number by 8 and collecting the remainders in reverse order.
8 | 417
8 | 52 — 1
8 | 6 – 4
So, (417)10= (641)8

14. Convert the hexadecimal number (1E2)16 to decimal:
a) 480
b) 483
c) 482
d) 484
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base index along with the value at that index position.
(1E2)16 = 1 * 162 + 14 * 161 + 2 * 160 (Since, E = 14)
= 256 + 224 + 2 = (482)10

15. (170)10 is equivalent to
a) (FD)16
b) (DF)16
c) (AA)16
d) (AF)16
Explanation: Hexadecimal equivalent of decimal number is obtained by dividing the number by 16 and collecting the remainders in reverse order.
16 | 170
16 | 10 – 10
Hence, (170)10 = (AA)16

16. Convert (214)8 into decimal:
a) (140)10
b) (141)10
c) (142)10
d) (130)10
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
(214)8 = 2 * 8v + 1 * 81 + 4 * 80
= 128 + 8 + 4 = (140)10

17. Convert (0.345)10 into an octal number:
a) (0.16050)8
b) (0.26050)8
c) (0.19450)8
d) (0.24040)8
Explanation: Converting decimal fraction into octal number is achieved by multiplying the fraction part by 8 everytime and collecting the integer part of the result, unless the result is 1.
0.345*8 = 2.76 2
0.760*8 = 6.08 6
00.08*8 = 0.64 0
0.640*8 = 5.12 5
0.120*8 = 0.96 0
So, (0.345)10 = (0.26050)8

18. Convert the binary number (01011.1011)2 into decimal:
a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.7893)10
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along with the value at that index position.
(01011)2 = 0 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 = 11
(1011)2 = 1 * 2-1 + 0 * 2-2 + 1 * 2-3 + 1 * 2-4 = 0.6875
So, (01011.1011)2 = (11.6875)10

19. Octal to binary conversion: (24)8 =?
a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2
Explanation: Each digit of the octal number is expressed in terms of group of 3 bits. Thus, the binary equivalent of the octal number is obtained.
(24)8 = (010100)2

20. Convert binary to octal: (110110001010)2 =?
a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8
Explanation: The binary equivalent is segregated into groups of 3 bits, starting from left. And then for each group, the respective digit is written. Thus, the octal equivalent is obtained.
(110110001010)2 = (6612)8

21. What is the addition of the binary numbers 11011011010 and 010100101?
a) 0111001000
b) 1100110110
c) 11101111111
d) 10011010011
Explanation: The rules for Binary Addition are :
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0 ( Carry 1)

```       1

1 1 0 1 1 0 1 1 0 1 0

+ 0 0 0 1 0 1 0 0 1 0 1
_______________________
1 1 1 0 1 1 1 1 1 1 1
_______________________```

22. Perform binary addition: 101101 + 011011 = ?
a) 011010
b) 1010100
c) 101110
d) 1001000
Explanation:The rules for Binary Addition are :
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0 ( Carry 1)

``` 1 1 1 1 1 1
1 0 1 1 0 1
+ 0 1 1 0 1 1
_______________
1 0 0 1 0 0 0
_______________```

Therefore, the addition of 101101 + 011011 = 1001000.

23. Perform binary subtraction: 101111 – 010101 = ?
a) 100100
b) 010101
c) 011010
d) 011001
Explanation: The rules for Binary Subtraction are :
0 – 0 = 0
0 – 1 = 1 ( Borrow 1)
1 – 0 = 1
1 – 1 = 0

```  1 0 1 1 1 1
- 0 1 0 1 0 1
____________
0 1 1 0 1 0
_____________```

Therefore, The subtraction of 101111 – 010101 = 011010.

24. Binary subtraction of 100101 – 011110 is
a) 000111
b) 111000
c) 010101
d) 101010
Explanation: The rules for Binary Subtraction are :
0 – 0 = 0
0 – 1 = 1 ( Borrow 1)
1 – 0 = 1
1 – 1 = 0

```  1 0 0 1 0 1
- 0 1 1 1 1 0
___________
0 0 0 1 1 1
___________```

Therefore, The subtraction of 100101 – 011110 = 000111.

25. Perform multiplication of the binary numbers: 01001 × 01011 = ?
a) 001100011
b) 110011100
c) 010100110
d) 101010111
Explanation: The rules for binary multiplication are:
0 * 0 = 0
0 * 1 = 0
1 * 0 = 0
1 * 1 = 1

```               0 1 0 0 1
x 0 1 0 1 1
____________
0 1 0 0 1
0 1 0 0 1 0
0 0 0 0 0 0 0
0 1 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0
___________________
0 0 1 1 0 0 0 1 1
___________________```

Therefore, 01001 × 01011 = 001100011.

26. 100101 × 0110 = ?
a) 1011001111
b) 0100110011
c) 101111110
d) 0110100101
Explanation: The rules for binary multiplication are:
0 * 0 = 0
0 * 1 = 0
1 * 0 = 0
1 * 1 = 1

```                      1 0 0 1 0 1
x        0 1 1 0
___________
0 0 0 0 0 0
1 0 0 1 0 1 0
1 0 0 1 0 1 0 0
0 0 0 0 0 0 0 0 0
__________________
0 1 1 0 1 1 1 1 0
___________________```

Therefore, 100101 x 0110 = 011011110.

27. On multiplication of (10.10) and (01.01), we get
a) 101.0010
b) 0010.101
c) 011.0010
d) 110.0011
Explanation: The rules for binary multiplication are:
0 * 0 = 0
0 * 1 = 0
1 * 0 = 0
1 * 1 = 1

```           1 0.1 0
x    0 1.0 1
__________
1 0 1 0
0 0 0 0 0
1 0 1 0 0 0
0 0 0 0 0 0 0
_______________
0 1 1.0 0 1 0
_________________```

Therefore, 10.10 x 01.01 = 011.0010.

28. Divide the binary numbers: 111101 ÷ 1001 and find the remainder
a) 0010
b) 1010
c) 1100
d) 0011
Explanation: Binary Division is accomplished using long division method.

```1 0 0 1 ) 1 1 1 1 0 1 ( 1 1
1 0 0 1
__________
0 1 1 0 0
1 0 0 1
___________
0 1 1 1```

Therefore, the remainder of 111101 ÷ 1001 = 0111.

29. Divide the binary number (011010000) by (0101) and find the quotient
a) 100011
b) 101001
c) 110010
d) 010001
Explanation:

```0 1 0 1 ) 0 1 1 0 1 0 0 0 0 ( 0 1 0 1 1 1
0 0 0 0
_____________________
0 1 1 0 1
0 0 1 0 1
______________
0 1 0 0 0 0
0 0 0 0 0 0
______________________
1 0 0 0 0
0 0 1 0 1
____________________
0 1 0 1 1 0
0 0 0 1 0 1
____________________
1 0 0 0 1 0
0 0 0 1 0 1
________________________
1 1 1 0 1 0
0 0 0 1 0 1
________________________
1 0 1 0 1
0 0 1 0 1
________________________
1 0 0 0 0```

Therefore, the quotient of 011010000 ÷ 1001 = 101001.

30. Binary subtraction of 101101 – 001011 = ?
a) 100010
b) 010110
c) 110101
d) 101100
Explanation: The rules for binary subtraction are:
0 – 0 = 0
0 – 1 = 1 ( Borrow 1)
1 – 0 = 1
1 – 1 = 0

```1 0 1 1 0 1
- 0 0 1 0 1 1
____________
1 0 0 0 1 0
____________

```

31. 1’s complement of 1011101 is ____________
a) 0101110
b) 1001101
c) 0100010
d) 1100101
Explanation: 1’s complement of a binary number is obtained by reversing the binary bits. All the 1’s to 0’s and 0’s to 1’s.
Thus, 1’s complement of 1011101 = 0100010.

32. 2’s complement of 11001011 is ____________
a) 01010111
b) 11010100
c) 00110101
d) 11100010
Explanation: 2’s complement of a binary number is obtained by finding the 1’s complement of the number and then adding 1 to it.
2’s complement of 11001011 = 00110100 + 1 = 00110101.

33. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________
a) 01001
b) 11010
c) 10101
d) 10100
Explanation: Steps For Subtraction using 1’s complement are:
-> 1’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and 1 is added to the last bit of the result.
-> Else, if there is no carry, then 1’s complement of the result is found out and a ‘-’ sign preceeds the result.

```                                             1 1 1
Minuend -              1 1 1 1 0
1’s complement of subtrahend -              1 0 1 0 1
____________
Carry over -     1         1 0 0 1 1
1
_____________
1 0 1 0 0```

34. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ____________
a) 0111001
b) 1100101
c) 0110110
d) 1000011
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.

```      1’s complement of subtrahend -              1 1 0 1 0 0 1
_________________
1 1 1
Minuend -              1 0 1 1 0 0 1
2’s complement of subtrahend -              1 1 0 1 0 1 0
_________________

Carry over -    1         1 0 0 0 0 1 1

35. On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________
a) 1101100
b) 011101
c) 11010101
d) 11010111
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.

```      1’s complement of subtrahend -              1 1 0 0 1 1
_________________
Minuend -              1 0 1 0 0 1
2’s complement of subtrahend -              1 1 0 1 0 0
_________________
Carry over -    1         0 1 1 1 0 1

36. On addition of 28 and 18 using 2’s complement, we get ____________
a) 00101110
b) 0101110
c) 00101111
d) 1001111
Explanation: Steps for Binary Addition Using 2’s complement:
-> The binary equivalent of the two numbers are obtained and added using the rules of binary addition.

```Augend -        0   0 1 1 1 0 0

Addend -        0   0 1 0 0 1 0
_________________
0   1 0 1 1 1 0

Answer: 0  1 0 1 1 1 0```

37. On addition of +38 and -20 using 2’s complement, we get ____________
a) 11110001
b) 100001110
c) 010010
d) 110101011
Explanation: Steps for Binary Addition Using 2’s complement:
-> The 2’s complement of the addend is found out and added to the first number.
-> The result is the 2’s complement of the sum obtained.

```                     Augend -           0 1 0 0 1 1 0
2’s Complement of Subtrahend:           1 1 0 1 1 0 0
_________________
1         0 0 1 0 0 1 0

Answer: 0 1 0 0 1 0```

38. On addition of -46 and +28 using 2’s complement, we get ____________
a) -10010
b) -00101
c) 01011
d) 0100101
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is 28 and Subtrahend is -46.

```                            Augend -           0 0 1 1 1 0 0   .....(a)
2’s Complement of Subtrahend:            1 0 1 0 0 1 0   .....(b)
_________________
Addiing (a) and (b):            1 1 0 1 1 1 0
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.
0 0 1 0 0 0 1
+               1
_________________
0 0 1 0 0 1 0

Answer: - 1 0 0 1 0```

39. On addition of -33 and -40 using 2’s complement, we get ____________
a) 1001110
b) -110101
c) 0110001
d) -1001001
Explanation: The BCD form is written of the two given numbers, in their signed form. After which, normal binary addition is performed.
Augend is -40 and Subtrahend is -33.

```                            Augend -           1    0 1 0 0 0 0 1   .....(a)
2’s Complement of Subtrahend:            1    1 0 1 1 0 0 1   .....(b)
______________________
Addiing (a) and (b):           1 0   1 0 0 1 0 0 0
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.
1 0 0 1 0 0 0
+               1
_________________
1 0 0 1 0 0 1

40. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds the result.

```         1’s complement of subtrahend -        1 0 0 0 1 1
Minuend -        0 1 1 1 0 1
2’s complement of subtrahend -        1 0 0 1 0 0
____________________

Carry over -    1   0 0 0 0 0 1

41. If the number of bits in the sum exceeds the number of bits in each added numbers, it results in _________
a) Successor
b) Overflow
c) Underflow
d) Predecessor
Explanation: If the number of bits in the sum exceeds the number of bits in each added numbers, it results in overflow and is also known as excess-one. In case of any arithmetic operation, if the result has less number of bits than the operands, then it is known as underflow condition.

42. An overflow is a _________
a) Hardware problem
b) Software problem
c) User input problem
d) Input Output Error
Explanation: An overflow is a software problem which occurs when the processor cannot handle the result properly when it produces an out of the range output.

43. An overflow occurs in _________
a) MSD position
b) LSD position
c) Middle position
d) Signed Bit
Explanation: An overflow occurs at Most Significant Digit position. It occurs when the processor cannot handle the result properly when it produces an out of the range output.

44. Logic circuitry is used to detect _________
a) Underflow
b) MSD
c) Overflow
d) LSD
Explanation: To check the overflow logic circuitry is used in each case. Overflow occurs when the processor cannot handle the result properly when it produces an out of the range output.

45. 1’s complement can be easily obtained by using _________
a) Comparator
b) Inverter
d) Subtractor
Explanation: With the help of inverter the 1’s complement is easily obtained. Since, during the operation of 1’s complement 1 is converted into 0 and vice-versa and this is well suited for the inverter.

46. The advantage of 2’s complement system is that _________
a) Only one arithmetic operation is required
b) Two arithmetic operations are required
c) No arithmetic operations are required
d) Different Arithmetic operations are required
Explanation: The advantage of 2’s complement is that only one arithmetic operation is required for 2’s complement’s operation and that is only addition. Just by adding a 1 bit to 1’s complement, we get 2’s complement.

47. The 1’s complements requires _________
a) One operation
b) Two operations
c) Three operations
d) Combined Operations
Explanation: Only one operation is required for 1’s complement operation. This includes only inversion of 1’s to 0’s and 0’s to 1’s.

48. Which one is used for logical manipulations?
a) 2’s complement
b) 9’s complement
c) 1’s complement
d) 10’s complement
Explanation: For logical manipulations, 1’s complement is used, as all logical operations take place with binary numbers.

49. For arithmetic operations only _________
a) 1’s complement is used
b) 2’s complement
c) 10’s complement
d) 9’s complement
Explanation: Only 2’s complement is used for arithmetic operations, as it is more fast.

50. The addition of +19 and +43 results as _________ in 2’s complement system.
a) 11001010
b) 101011010
c) 00101010
d) 0111110
Explanation: The decimal numbers are converted to their respective binary equivalent and then the binary addition rules are applied.

51. Binary coded decimal is a combination of __________
a) Two binary digits
b) Three binary digits
c) Four binary digits
d) Five binary digits
Explanation: Binary coded decimal is a combination of 4 binary digits. For example-8421.

52. The decimal number 10 is represented in its BCD form as __________
a) 10100000
b) 01010111
c) 00010000
d) 00101011
Explanation: The decimal number 10 is represented in its BCD form as 0001 0000, in accordance to 8421 for each of the two digits.

53. Add the two BCD numbers: 1001 + 0100 = ?
a) 10101111
b) 01010000
c) 00010011
d) 00101011
Explanation: Firstly, Add the 1001 and 0100. We get 1101 as output but it’s not in BCD form. So, we add 0110 (i.e. 6) with 1101. As a result we get 10011 and it’s BCD form is 0001 0011.

54. Carry out BCD subtraction for (68) – (61) using 10’s complement method.
a) 00000111
b) 01110000
c) 100000111
d) 011111000
Explanation: First the two numbers are converted into their respective BCD form using 8421 sequence. Then binary subtraction is carried out.

55. Code is a symbolic representation of __________ information.
a) Continuous
b) Discrete
c) Analog
d) Both continuous and discrete
Explanation: Code is a symbolic representation of discrete information, which may be present in the form of numbers, letters or physical quantities. Mostly, it is represented using a particular number system like decimal or binary and such like.

56. When numbers, letters or words are represented by a special group of symbols, this process is called __________
a) Decoding
b) Encoding
c) Digitizing
d) Inverting
Explanation: When numbers, letters or words are represented by a special group of symbols, this process is called encoding. Encoding in the sense of fetching the codes or words in a computer. It is done to secure the transmission of information.

57. A three-digit decimal number requires ________ for representation in the conventional BCD format.
a) 3 bits
b) 6 bits
c) 12 bits
d) 24 bits
Explanation: The number of bits needed to represent a given decimal number is always greater than the number of bits required for a straight binary encoding of the same. Hence, a three digit decimal number requires 12 bits for representation in BCD format.

58. How many bits would be required to encode decimal numbers 0 to 9999 in straight binary codes?
a) 12
b) 14
c) 16
d) 18
Explanation: Total number of decimals to be represented = 10000 = 104 = 2n (where n is the number of bits required) = 213.29. Therefore, the number of bits required for straight binary encoding = 14.

59. The excess-3 code for 597 is given by __________
a) 100011001010
b) 100010100111
c) 010110010111
d) 010110101101
Explanation: The addition of ‘3’ to each digit yields the three new digits ‘8’, ’12’ and ’10’. Hence, the corresponding four-bit binary equivalents are 100011001010, in accordance to 8421 format.

60. The decimal equivalent of the excess-3 number 110010100011.01110101 is _____________
a) 970.42
b) 1253.75
c) 861.75
d) 1132.87
Explanation: The conversion of binary numbers into digits ‘1100’, ‘1010’, ‘0011’, ‘0111’ and ‘0101’ gives ’12’, ‘5’, ‘3’, ‘7’ and ‘5’ respectively. Hence, the decimal number is 970.42.

#### Module 02

1.What is the difference between the 54XX and 74XX series of TTL logic gates?
a.54XX is faster.
b.54XX is slower.
c.54XX has a wider power supply and expanded temperature range.
d.54XX has a narrower power supply and contracted temperature range.

2.An open collector output can ________ current, but it cannot ________.
a.sink, source current
b.source, sink current
c.sink, a source voltage
d.source, sink voltage

3.Why is a decoupling capacitor needed for TTL ICs and where should it be connected?
a.to block dc, connect to input pins
b.to reduce noise, connect to input pins
c.to reduce the effects of noise, connect between power supply and ground

4.Using the schematic diagram of a TTL NAND gate, determine the state of each transistor (ON or OFF) when all inputs are high.
a.Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
b.Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
c.Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
d.Q1-OFF, Q2-ON, Q3-OFF, Q4-ON

5.If all inputs to a TTL NAND gate are low, what is the ON, OFF condition of each transistor in the circuit?
a.Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
b.Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
c.Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
d.Q1-OFF, Q2-ON, Q3-OFF, Q4-ON

6.What is the advantage of using low-power Schottky (LS) over standard TTL logic?
a.more power dissipation
b.less power dissipation
c.cost is less
d.cost is more

7.When is a level-shifter circuit needed in interfacing logic?
a.A level shifter is always needed.
b.A level shifter is never needed.
c.when the supply voltages are the same
d.when the supply voltages are different

8.A TTL totem-pole circuit is designed so that the output transistors:
a.are always on together
b.provide linear phase splitting
c.provide voltage regulation
d.are never on together

9.The most common TTL series ICs are:
a.E-MOSFET
b.7400
d.AC00

11. Transistor–transistor logic (TTL) is a class of digital circuits built from ____________
a) JFET only
b) Bipolar junction transistors (BJT)
c) Resistors
d) Bipolar junction transistors (BJT) and resistors
Explanation: Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and resistors. However, resistors have a small role to play and both logic gating and amplifying functions are performed by the transistors.

12. TTL is called transistor–transistor logic because both the logic gating function and the amplifying function are performed by ____________
a) Resistors
b) Bipolar junction transistors
c) One transistor
d) Resistors and transistors respectively
Explanation: TTL is called transistor–transistor logic because both the logic gating function and the amplifying function are performed by bipolar junction transistors (BJTs).

13. TTL was invented in 1961 by ____________
a) Baker clamp
b) James L. Buie
c) Chris Brown
d) Frank Wanlass
Explanation: TTL was invented in 1961 by James L Buie.

14. The full form of TCTL is ____________
a) Transistor-coupled transistor logic
b) Transistor-capacitor transistor logic
c) Transistor-complemented transistor logic
d) Transistor-complementary transistor logic
Explanation: The full form of TCTL is transistor-coupled transistor logic.

15. The _______ ancestor to the first personal computers.
a) PARAM 1
b) SATYAM 1
c) KENBAK 1
d) MITS Altair
Explanation: The KENBAK 1, ancestor to the first personal computers.

16. TTL inputs are the emitters of a ____________
a) Transistor-transistor logic
b) Multiple-emitter transistor
c) Resistor-transistor logic
d) Diode-transistor logic
Explanation: TTL inputs are the emitters of a multiple-emitter transistor.

17. TTL is a ____________
a) Current sinking
b) Current sourcing
c) Voltage sinking
d) Voltage sourcing
Explanation: Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring them to a logic 0 level. Current Sink means it accepts current coming out from a source.

18. Standard TTL circuits operate with a __ volt power supply.
a) 2
b) 4
c) 5
d) 3
Explanation: Standard TTL circuits operate with a 5-volt power supply.

19. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
a) Less
b) More
c) Equal
d) Very High
Explanation: TTL devices consume substantially more power than equivalent CMOS devices at rest. Thus, CMOS devices are faster than TTL devices.

20. A TTL gate may operate inadvertently as an ____________
a) Digital amplifier
b) Analog amplifier
c) Inverter
d) Regulator
Explanation: A TTL gate may operate inadvertently as an analog amplifier if the input is connected to a slowly changing input signal that traverses the unspecified region from 0.7V to 3.3V.

21. The speed of ______ circuits is limited by the tendency of common emitter circuits to go into saturation.
a) TTL
b) ECL
c) RTL
d) DTL
Explanation: The speed of TTL circuits is limited by the tendency of common emitter circuits to go into saturation due to the injection of minority carriers into the collector region. Hence, it functions slowly compared to CMOS devices.

22. The full form of CMOS is ____________
a) Capacitive metal oxide semiconductor
b) Capacitive metallic oxide semiconductor
c) Complementary metal oxide semiconductor
d) Complemented metal oxide semiconductor
Explanation: The full form of CMOS is complementary metal oxide semiconductor. In this type of device, both n-type and p-type transistors are used in a complementary way.

23. The full form of COS-MOS is ____________
a) Complementary symmetry metal oxide semiconductor
b) Complementary systematic metal oxide semiconductor
c) Capacitive symmetry metal oxide semiconductor
d) Complemented systematic metal oxide semiconductor
Explanation: The full form of COS-MOS is complementary systematic metal oxide semiconductor. In this type of device, both n-type and p-type transistors are used in a complementary way. Usually, the transistors used are MOSFETs.

24. CMOS is also sometimes referred to as ____________
a) Capacitive metal oxide semiconductor
b) Capacitive symmetry metal oxide semiconductor
c) Complementary symmetry metal oxide semiconductor
d) Complemented symmetry metal oxide semiconductor
Explanation: CMOS is also sometimes referred to as complementary systematic metal oxide–semiconductor (COS-MOS). In this type of device, both n-type and p-type transistors are used in a complementary way. Usually, the transistors used are MOSFETs.

25. CMOS technology is used in ____________
a) Inverter
b) Microprocessor
c) Digital logic
d) Both microprocessor and digital logic
Explanation: CMOS technology is used in Microprocessor, Microcontroller, static RAM and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters and highly integrated transceivers for many types of communication.

26. Two important characteristics of CMOS devices are ____________
a) High noise immunity
b) Low static power consumption
c) High resistivity
d) Both high noise immunity and low static power consumption
Explanation: Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Since one transistor of the pair is always off and the series combination draws significant power only momentarily during switching between on and off states. Also, the performance of CMOS is not altered with the presence of noise and thus it has high noise immunity.

27. CMOS behaves as a/an ____________
b) Subtractor
c) Inverter
d) Comparator
Explanation: Since, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high and when the input is high, the output is low. Because of this behaviour of input and output, the CMOS circuit’s output is the inverse of the input. Whereas, adders and subtractors are combinational circuits.

28. An important characteristic of a CMOS circuit is the ____________
a) Noise immunity
b) Duality
c) Symmetricity
d) Noise Margin
Explanation: An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. Due to the presence of two different types of transistors, the device has the complementary function.

29. CMOS logic dissipates _______ power than NMOS logic circuits.
a) More
b) Less
c) Equal
d) Very High
Explanation: CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching (“dynamic power”). Thus, CMOS has less power consumption and is more efficient.

30. Semiconductors are made of ____________
a) Ge and Si
b) Si and Pb
c) Ge and Pb
d) Pb and Au
Explanation: Semiconductors are made of Silicon (Si) and Germanium (Ge). Semiconductors are devices having conductivity between conductors and insulators.

31. Which chip were the first RTC and CMOS RAM chips to be used in early IBM computers, capable of storing a total of 64 bytes?
a) The Samsung 146818
b) The Samsung 146819
c) The Motorola 146818
d) The Motorola 146819
Explanation: The Motorola 146818 was the first RTC and CMOS RAM chip to be used in early IBM computers; capable of storing a total of 64 bytes.

32. The output of a logic gate is 1 when all the input are at logic 0 as shown below:

`INPUT`
`OUTPUT`
`A`
`B`
`C`
`0`
`0`
`1`
`0`
`1`
`0`
`1`
`0`
`0`
`1`
`1`
`0`
`INPUT`
`OUTPUT`
`A`
`B`
`C`
`0`
`0`
`1`
`0`
`1`
`0`
`1`
`0`
`0`
`1`
`1`
`1`

The gate is either _________
a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is NOR. The output of a logic gate is 1 when all inputs are at logic 0 or all inputs are at logic 1, then it is EX-NOR. (The truth tables for NOR and EX-NOR Gates are shown in above table).

33. The code where all successive numbers differ from their preceding number by single bit is __________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Explanation: The code where all successive numbers differ from their preceding number by single bit is gray code. It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next. BCD Code is one in which decimal digits are represented by a group of 4-bits each, whereas, in Excess-3 Code, the decimal numbers are incremented by 3 and then written in their BCD format.

34. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

35. How many AND gates are required to realize Y = CD + EF + G?
a) 4
b) 5
c) 3
d) 2
Explanation: To realize Y = CD + EF + G, two AND gates are required and two OR gates are required.

36. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
Explanation: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be 00.

37. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.

38. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
Explanation: An Universal Logic Gate is one which can generate any logic function and also the three basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic function and are thus Universal Logic Gates.

39. A full adder logic circuit will have __________
a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there. In case of half adder circuit, there are only two inputs bits and two outputs (SUM and CARRY).

40. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
Explanation: There are three product terms. So, three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.

41. Which of the following are known as universal gates?
a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates, and also they can generate the 3 basic gates AND, OR and NOT.

42. The gates required to build a half adder are __________
a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
Explanation: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the SUM of the two input bits whereas AND outputs the CARRY of the two input bits.

43. The universal gate is ………………
a.NAND gate
b.OR gate
c.AND gate
d.None of the above

44.The inverter is ……………
a.NOT gate
b.OR gate
c.AND gate
d.None of the above

45. The inputs of a NAND gate are connected together. The resulting circuit is ………….
a.OR gate
b.AND gate
c.NOT gate
d.None of the above

46. The NOR gate is OR gate followed by ………………
a.AND gate
b.NAND gate
c.NOT gate
d.None of the above

47. The NAND gate is AND gate followed by …………………
a.NOT gate
b.OR gate
c.AND gate
d.None of the above

48. Digital circuit can be made by the repeated use of ………………
a.OR gates
b.NOT gates
c.NAND gates
d.None of the above

49. The only function of NOT gate is to ……………..
a.Stop signal
b.Invert input signal
c.Act as a universal gate
d.None of the above

50. When an input signal 1 is applied to a NOT gate, the output is ………………
a.0
b.1
c.Either 0 & 1
d.None of the above

51. In Boolean algebra, the bar sign (-) indicates ………………..
a.OR operation
b.AND operation
c.NOT operation
d.None of the above

52. An OR gate has 4 inputs. One input is high and the other three are low. The output is …….
a.Low
b.High
c.alternately high and low
d.may be high or low depending on relative magnitude of inputs

53. Both OR and AND gates can have only two inputs.
a.True
b.False

54. The output will be a LOW for any case when one or more inputs are zero in a/an …………
a.OR Gate
b.NOT Gate
c.AND Gate
d.NAND Gate

55. A single transistor can be used to build ………….. gates .
a.OR Gate
b.NOT Gate
c.AND Gate
d.NAND Gate

56. The logic gate that will have HIGH or “1” at its output when any one of its inputs is HIGH is a/an …………… gate.
a.OR Gate
b.NOT Gate
c.AND Gate
d.NAND Gate

57. …………. NAND circuits are contained in a 7400 NAND IC.
a.1
b.2
c.4
d.8

58. Exclusive-OR (XOR) logic gates can be constructed from ………..logic gates.
a.OR gates only
b.AND gates and NOT gates
c.AND gates, OR gates, and NOT gates
d.OR gates and NOT gates

59. ……….. truth table entries are necessary for a four-input circuit.
a.4
b.8
c.12
d.16

60. A NAND gate has …….. inputs and ……. output.
a.LOW inputs and LOW outputs
b.HIGH inputs and HIGH outputs
c.LOW inputs and HIGH outputs
d.None of these

61. The basic logic gate whose output is the complement of the input is ………….
a.OR gate
b.AND gate
c.INVERTER gate
d.Comparator

62. ……….. input values will cause an AND logic gate to produce a HIGH output.
a.At least one input is HIGH
b.At least one input is LOW
c.All inputs are HIGH
d.All inputs are LOW

63. In boolean algebra, the OR operation is performed by which properties?
a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C & A*(B*C) = (A*B)*C.
The expression for Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.

64. The expression for Absorption law is given by _________
a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A
Explanation: The expression for Absorption Law is given by: A+AB = A.
Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as per 1’s Property).

65. According to boolean law: A + 1 = ?
a) 1
b) A
c) 0
d) A’
Explanation: A + 1 = 1, as per 1’s Property.

66. The involution of A is equal to _________
a) A
b) A’
c) 1
d) 0
Explanation: The involution of A means double inversion of A (i.e. A”) and is equal to A.
Proof: ((A)’)’ = A

67. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
Explanation: A(A + B) = AA + AB (By Distributive Property) = A + AB (A.A = A By Commutative Property) = A(1 + B) = A*1 (1 + B = 1 by 1’s Property) = A.

68. DeMorgan’s theorem states that _________
a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.

69. (A + B)(A’ * B’) = ?
a) 1
b) 0
c) AB
d) AB’
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.

70. Complement of the expression A’B + CD’ is _________
a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By DeMorgan’s Theorem) = (A” + B’)(C’ + D”) (By DeMorgan’s Theorem) = (A + B’)(C’ + D).

71. Simplify Y = AB’ + (A’ + B)C.
a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
Explanation: Y = AB’ + (A’ + B)C = AB’ + (AB’)’C = (AB’ + C)( AB’ + AB’) = (AB’ + C).1 = (AB’ + C).

72. The boolean function A + BC is a reduced form of ____________
a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC (By Commutative Property) = A(1 + C + B) + BC = A + BC (1 + B + C =1 By 1’s Property).

1.What is the difference between the 54XX and 74XX series of TTL logic gates?
a.54XX is faster.
b.54XX is slower.
c.54XX has a wider power supply and expanded temperature range.
d.54XX has a narrower power supply and contracted temperature range.

2.An open collector output can ________ current, but it cannot ________.
a.sink, source current
b.source, sink current
c.sink, source voltage
d.source, sink voltage

3.Why is a decoupling capacitor needed for TTL ICs and where should it be connected?
a.to block dc, connect to input pins
b.to reduce noise, connect to input pins
c.to reduce the effects of noise, connect between power supply and ground

4.Using the schematic diagram of a TTL NAND gate, determine the state of each transistor (ON or OFF) when all inputs are high.
a.Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
b.Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
c.Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
d.Q1-OFF, Q2-ON, Q3-OFF, Q4-ON

5.If all inputs to a TTL NAND gate are low, what is the ON, OFF condition of each transistor in the circuit?
a.Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
b.Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
c.Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
d.Q1-OFF, Q2-ON, Q3-OFF, Q4-ON

6.What is the advantage of using low-power Schottky (LS) over standard TTL logic?
a.more power dissipation
b.less power dissipation
c.cost is less
d.cost is more

7.When is a level-shifter circuit needed in interfacing logic?
a.A level shifter is always needed.
b.A level shifter is never needed.
c.when the supply voltages are the same
d.when the supply voltages are different

8.A TTL totem-pole circuit is designed so that the output transistors:
a.are always on together
b.provide linear phase splitting
c.provide voltage regulation
d.are never on together

9.The most common TTL series ICs are:
a.E-MOSFET
b.7400
d.AC00

10.Fan-out is determined by taking the ________ result(s) of ________.

a.smaller,
b.larger,
c.smaller,
d.average,

11. Transistor–transistor logic (TTL) is a class of digital circuits built from ____________
a) JFET only
b) Bipolar junction transistors (BJT)
c) Resistors
d) Bipolar junction transistors (BJT) and resistors
Explanation: Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and resistors. However, resistors have a small role to play and both logic gating and amplifying functions are performed by the transistors.

12. TTL is called transistor–transistor logic because both the logic gating function and the amplifying function are performed by ____________
a) Resistors
b) Bipolar junction transistors
c) One transistor
d) Resistors and transistors respectively
Explanation: TTL is called transistor–transistor logic because both the logic gating function and the amplifying function are performed by bipolar junction transistors (BJTs).

13. TTL was invented in 1961 by ____________
a) Baker clamp
b) James L. Buie
c) Chris Brown
d) Frank Wanlass
Explanation: TTL was invented in 1961 by James L Buie.

14. The full form of TCTL is ____________
a) Transistor-coupled transistor logic
b) Transistor-capacitor transistor logic
c) Transistor-complemented transistor logic
d) Transistor-complementary transistor logic
Explanation: The full form of TCTL is transistor-coupled transistor logic.

15. The _______ ancestor to the first personal computers.
a) PARAM 1
b) SATYAM 1
c) KENBAK 1
d) MITS Altair
Explanation: The KENBAK 1, ancestor to the first personal computers.

16. TTL inputs are the emitters of a ____________
a) Transistor-transistor logic
b) Multiple-emitter transistor
c) Resistor-transistor logic
d) Diode-transistor logic
Explanation: TTL inputs are the emitters of a multiple-emitter transistor.

17. TTL is a ____________
a) Current sinking
b) Current sourcing
c) Voltage sinking
d) Voltage sourcing
Explanation: Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring them to a logic 0 level. Current Sink means it accepts current coming out from a source.

18. Standard TTL circuits operate with a __ volt power supply.
a) 2
b) 4
c) 5
d) 3
Explanation: Standard TTL circuits operate with a 5-volt power supply.

19. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
a) Less
b) More
c) Equal
d) Very High
Explanation: TTL devices consume substantially more power than equivalent CMOS devices at rest. Thus, CMOS devices are faster than TTL devices.

20. A TTL gate may operate inadvertently as an ____________
a) Digital amplifier
b) Analog amplifier
c) Inverter
d) Regulator
Explanation: A TTL gate may operate inadvertently as an analog amplifier if the input is connected to a slowly changing input signal that traverses the unspecified region from 0.7V to 3.3V.

21. The speed of ______ circuits is limited by the tendency of common emitter circuits to go into saturation.
a) TTL
b) ECL
c) RTL
d) DTL
Explanation: The speed of TTL circuits is limited by the tendency of common emitter circuits to go into saturation due to the injection of minority carriers into the collector region. Hence, it functions slowly compared to CMOS devices.

22. The full form of CMOS is ____________
a) Capacitive metal oxide semiconductor
b) Capacitive metallic oxide semiconductor
c) Complementary metal oxide semiconductor
d) Complemented metal oxide semiconductor
Explanation: The full form of CMOS is complementary metal oxide semiconductor. In this type of device, both n-type and p-type transistors are used in a complementary way.

23. The full form of COS-MOS is ____________
a) Complementary symmetry metal oxide semiconductor
b) Complementary systematic metal oxide semiconductor
c) Capacitive symmetry metal oxide semiconductor
d) Complemented systematic metal oxide semiconductor
Explanation: The full form of COS-MOS is complementary systematic metal oxide semiconductor. In this type of device, both n-type and p-type transistors are used in a complementary way. Usually, the transistors used are MOSFETs.

24. CMOS is also sometimes referred to as ____________
a) Capacitive metal oxide semiconductor
b) Capacitive symmetry metal oxide semiconductor
c) Complementary symmetry metal oxide semiconductor
d) Complemented symmetry metal oxide semiconductor
Explanation: CMOS is also sometimes referred to as complementary systematic metal oxide–semiconductor (COS-MOS). In this type of device, both n-type and p-type transistors are used in a complementary way. Usually, the transistors used are MOSFETs.

25. CMOS technology is used in ____________
a) Inverter
b) Microprocessor
c) Digital logic
d) Both microprocessor and digital logic
Explanation: CMOS technology is used in Microprocessor, Microcontroller, static RAM and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters and highly integrated transceivers for many types of communication.

26. Two important characteristics of CMOS devices are ____________
a) High noise immunity
b) Low static power consumption
c) High resistivity
d) Both high noise immunity and low static power consumption
Explanation: Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Since one transistor of the pair is always off and the series combination draws significant power only momentarily during switching between on and off states. Also, the performance of CMOS is not altered with the presence of noise and thus it has high noise immunity.

27. CMOS behaves as a/an ____________
b) Subtractor
c) Inverter
d) Comparator
Explanation: Since, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high and when the input is high, the output is low. Because of this behaviour of input and output, the CMOS circuit’s output is the inverse of the input. Whereas, adders and subtractors are combinational circuits.

28. An important characteristic of a CMOS circuit is the ____________
a) Noise immunity
b) Duality
c) Symmetricity
d) Noise Margin
Explanation: An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. Due to the presence of two different types of transistors, the device has the complementary function.

29. CMOS logic dissipates _______ power than NMOS logic circuits.
a) More
b) Less
c) Equal
d) Very High
Explanation: CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching (“dynamic power”). Thus, CMOS has less power consumption and is more efficient.

30. Semiconductors are made of ____________
a) Ge and Si
b) Si and Pb
c) Ge and Pb
d) Pb and Au
Explanation: Semiconductors are made of Silicon (Si) and Germanium (Ge). Semiconductors are devices having conductivity between conductors and insulators.

31. Which chip were the first RTC and CMOS RAM chips to be used in early IBM computers, capable of storing a total of 64 bytes?
a) The Samsung 146818
b) The Samsung 146819
c) The Motorola 146818
d) The Motorola 146819
Explanation: The Motorola 146818 was the first RTC and CMOS RAM chip to be used in early IBM computers; capable of storing a total of 64 bytes.

32. The output of a logic gate is 1 when all the input are at logic 0 as shown below:

`INPUT`
`OUTPUT`
`A`
`B`
`C`
`0`
`0`
`1`
`0`
`1`
`0`
`1`
`0`
`0`
`1`
`1`
`0`
`INPUT`
`OUTPUT`
`A`
`B`
`C`
`0`
`0`
`1`
`0`
`1`
`0`
`1`
`0`
`0`
`1`
`1`
`1`

The gate is either _________
a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is NOR. The output of a logic gate is 1 when all inputs are at logic 0 or all inputs are at logic 1, then it is EX-NOR. (The truth tables for NOR and EX-NOR Gates are shown in above table).

33. The code where all successive numbers differ from their preceding number by single bit is __________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Explanation: The code where all successive numbers differ from their preceding number by single bit is gray code. It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next. BCD Code is one in which decimal digits are represented by a group of 4-bits each, whereas, in Excess-3 Code, the decimal numbers are incremented by 3 and then written in their BCD format.

34. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

35. How many AND gates are required to realize Y = CD + EF + G?
a) 4
b) 5
c) 3
d) 2
Explanation: To realize Y = CD + EF + G, two AND gates are required and two OR gates are required.

36. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
Explanation: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be 00.

37. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.

38. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
Explanation: An Universal Logic Gate is one which can generate any logic function and also the three basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic function and are thus Universal Logic Gates.

39. A full adder logic circuit will have __________
a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
Explanation: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there. In case of half adder circuit, there are only two inputs bits and two outputs (SUM and CARRY).

40. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
Explanation: There are three product terms. So, three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.

41. Which of the following are known as universal gates?
a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates, and also they can generate the 3 basic gates AND, OR and NOT.

42. The gates required to build a half adder are __________
a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
Explanation: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the SUM of the two input bits whereas AND outputs the CARRY of the two input bits.

43. The universal gate is ………………
a.NAND gate
b.OR gate
c.AND gate
d.None of the above

44.The inverter is ……………
a.NOT gate
b.OR gate
c.AND gate
d.None of the above

45. The inputs of a NAND gate are connected together. The resulting circuit is ………….
a.OR gate
b.AND gate
c.NOT gate
d.None of the above

46. The NOR gate is OR gate followed by ………………
a.AND gate
b.NAND gate
c.NOT gate
d.None of the above

47. The NAND gate is AND gate followed by …………………
a.NOT gate
b.OR gate
c.AND gate
d.None of the above

48. Digital circuit can be made by the repeated use of ………………
a.OR gates
b.NOT gates
c.NAND gates
d.None of the above

49. The only function of NOT gate is to ……………..
a.Stop signal
b.Invert input signal
c.Act as a universal gate
d.None of the above

50. When an input signal 1 is applied to a NOT gate, the output is ………………
a.0
b.1
c.Either 0 & 1
d.None of the above

51. In Boolean algebra, the bar sign (-) indicates ………………..
a.OR operation
b.AND operation
c.NOT operation
d.None of the above

52. An OR gate has 4 inputs. One input is high and the other three are low. The output is …….
a.Low
b.High
c.alternately high and low
d.may be high or low depending on relative magnitude of inputs

53. Both OR and AND gates can have only two inputs.
a.True
b.False

54. The output will be a LOW for any case when one or more inputs are zero in a/an …………
a.OR Gate
b.NOT Gate
c.AND Gate
d.NAND Gate

55. A single transistor can be used to build ………….. gates .
a.OR Gate
b.NOT Gate
c.AND Gate
d.NAND Gate

56. The logic gate that will have HIGH or “1” at its output when any one of its inputs is HIGH is a/an …………… gate.
a.OR Gate
b.NOT Gate
c.AND Gate
d.NAND Gate

57. …………. NAND circuits are contained in a 7400 NAND IC.
a.1
b.2
c.4
d.8

58. Exclusive-OR (XOR) logic gates can be constructed from ………..logic gates.
a.OR gates only
b.AND gates and NOT gates
c.AND gates, OR gates, and NOT gates
d.OR gates and NOT gates

59. ……….. truth table entries are necessary for a four-input circuit.
a.4
b.8
c.12
d.16

60. A NAND gate has …….. inputs and ……. output.
a.LOW inputs and LOW outputs
b.HIGH inputs and HIGH outputs
c.LOW inputs and HIGH outputs
d.None of these

61. The basic logic gate whose output is the complement of the input is ………….
a.OR gate
b.AND gate
c.INVERTER gate
d.Comparator

62. ……….. input values will cause an AND logic gate to produce a HIGH output.
a.At least one input is HIGH
b.At least one input is LOW
c.All inputs are HIGH
d.All inputs are LOW

63. In boolean algebra, the OR operation is performed by which properties?
a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C & A*(B*C) = (A*B)*C.
The expression for Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.

64. The expression for Absorption law is given by _________
a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A
Explanation: The expression for Absorption Law is given by: A+AB = A.
Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as per 1’s Property).

65. According to boolean law: A + 1 = ?
a) 1
b) A
c) 0
d) A’
Explanation: A + 1 = 1, as per 1’s Property.

66. The involution of A is equal to _________
a) A
b) A’
c) 1
d) 0
Explanation: The involution of A means double inversion of A (i.e. A”) and is equal to A.
Proof: ((A)’)’ = A

67. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
Explanation: A(A + B) = AA + AB (By Distributive Property) = A + AB (A.A = A By Commutative Property) = A(1 + B) = A*1 (1 + B = 1 by 1’s Property) = A.

68. DeMorgan’s theorem states that _________
a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.

69. (A + B)(A’ * B’) = ?
a) 1
b) 0
c) AB
d) AB’
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.

70. Complement of the expression A’B + CD’ is _________
a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By DeMorgan’s Theorem) = (A” + B’)(C’ + D”) (By DeMorgan’s Theorem) = (A + B’)(C’ + D).

71. Simplify Y = AB’ + (A’ + B)C.
a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
Explanation: Y = AB’ + (A’ + B)C = AB’ + (AB’)’C = (AB’ + C)( AB’ + AB’) = (AB’ + C).1 = (AB’ + C).

72. The boolean function A + BC is a reduced form of ____________
a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC (By Commutative Property) = A(1 + C + B) + BC = A + BC (1 + B + C =1 By 1’s Property).

#### Module 03

1. Which statement below best describes a Karnaugh map?
a) It is simply a rearranged truth table
b) The Karnaugh map eliminates the need for using NAND and NOR gates
c) Variable complements can be eliminated by using Karnaugh maps
d) A Karnaugh map can be used to replace Boolean rules
Explanation: K-map is simply a rearranged truth table. It is a pictorial representation of truth table having a specific number of cells or squares, where each cell represents a Maxterm or a Minterm.

2. Which of the examples below expresses the commutative law of multiplication?
a) A + B = B + A
b) A • B = B + A
c) A • (B • C) = (A • B) • C
d) A • B = B • A
Explanation: The commutative law of multiplication is (A * B) = (B * A).
The commutative law of addition is (A + B) = (B + A).
3. The Boolean expression Y = (AB)’ is logically equivalent to what single gate?
a) NAND
b) NOR
c) AND
d) OR
Explanation: If A and B are the input for AND gate the output is obtained as AB and after inversion we get (AB)’, which is the expression of NAND gate. NAND gate produces high output when any of the input is 0 and produces low output when all inputs are 1.

4. The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is referred to as:
a) A Karnaugh map
b) DeMorgan’s second theorem
c) The commutative law of addition
d) The associative law of multiplication
Explanation: DeMorgan’s Law: ~(P+Q) <=> (~P).(~Q) Also,
~(P.Q) <=> (~P)+(~Q).

5. The systematic reduction of logic circuits is accomplished by:
a) Symbolic reduction
b) TTL logic
c) Using Boolean algebra
d) Using a truth table
Explanation: The systematic reduction of logic circuits is accomplished by using boolean algebra.

6. Each “1” entry in a K-map square represents:
a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
Explanation: Each “1” entry in a K-map square represents a HIGH for each input truth table condition that produces a HIGH output. Thus, it represents a minterm.

7. Each “0” entry in a K-map square represents:
a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
Explanation: Each “0” entry in a K-map square represents a LOW output for all possible HIGH input conditions. Thus, it represents a Maxterm.

8. Which of the following statements accurately represents the two BEST methods of logic circuit simplification?
a) Actual circuit trial and error evaluation and waveform analysis
b) Karnaugh mapping and circuit waveform analysis
c) Boolean algebra and Karnaugh mapping
d) Boolean algebra and actual circuit trial and error evaluation
Explanation: The two BEST methods of logic circuit simplification are Boolean algebra and Karnaugh mapping. Boolean Algebra uses the Laws of Boolean Algebra for minimization of Boolean expressions while Karnaugh Map is a pictorial representation and reduction of the Boolean expression.

9. Looping on a K-map always results in the elimination of __________
a) Variables within the loop that appear only in their complemented form
b) Variables that remain unchanged within the loop
c) Variables within the loop that appear in both complemented and uncomplemented form
d) Variables within the loop that appear only in their uncomplemented form

10. Which of the following expressions is in the sum-of-products form?
a) (A + B)(C + D)
b) (A * B)(C * D)
c) A* B *(CD)
d) A * B + C * D
Explanation: Sum of product means that it is the sum of all product terms. Thus, the number is multiplied first and then it is added: A * B + C * D.

11. Which of the following is an important feature of the sum-of-products form of expressions?
a) All logic circuits are reduced to nothing more than simple AND and OR operations
b) The delay times are greatly reduced over other forms
c) No signal must pass through more than two gates, not including inverters
d) The maximum number of gates that any signal must pass through is reduced by a factor of two
Explanation: An important feature of the sum-of-products form of expressions in the given option is that all logic circuits are reduced to nothing more than simple AND and OR operations. Sum Of Product means it is the sum of product terms containing variables in complemented as well as uncomplemented forms.

12. Which of the following expressions is in the product-of-sums form?
a) (A + B)(C + D)
b) (AB)(CD)
c) AB(CD)
d) AB + CD
Explanation: (A + B)(C + D) represents the product-of-sums form.

13. In parts of the processor, adders are used to calculate ____________
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned
Explanation: Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used to calculate addresses, table indices, increment and decrement operators, and similar operations.

14. Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1
Explanation: Total number of inputs in a half adder is two. Since, an EXOR gates has 2 inputs and carry is connected with the input of EXOR gates. The output of half-adder is also 2, them being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.

15. In which operation carry is obtained?
a) Subtraction
c) Multiplication
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 – 1 = 1 (borrow 1).

16. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is given by A AND B.

17. If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the sum is given by A XOR B.

18. Half-adders have a major limitation in that they cannot __________
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.

a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference between them, while both have two outputs SUM and CARRY.

20. If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.

21. If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B) AND C, which is equivalent to (A AND B) OR (B AND C) OR (C AND A).

22. How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2 OR and 2 EXOR.

23. Half subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
Explanation: Half subtractor is a combinational circuit which is used to perform subtraction of two bits, namely minuend and subtrahend and produces two outputs, borrow and difference.

24. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output
Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because carry is taken into consideration during addition process.

25. How many outputs are required for the implementation of a subtractor?
a) 1
b) 2
c) 3
d) 4
Explanation: There are two outputs required for the implementation of a subtractor. One for the difference and another for borrow.

26. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
Explanation: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In both of the situation subtractor gives 0 as the output.

27. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
Explanation: The subtractor has two outputs BOROW and DIFFERENCE. Since, the difference output of a subtractor is given by AB’ + BA’ and this is the output of a XOR gate. So, the final difference output is AB’ + BA’.

28. Let A and B is the input of a subtractor then the borrow will be ___________
a) A AND B’
b) A’ AND B
c) A OR B
d) A AND B
Explanation: The borrow of a subtractor is received through AND gate whose one input is inverted. On that basis the borrow will be (A’ AND B).

29. What does minuend and subtrahend denotes in a subtractor?
a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits
Explanation: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the two inputs of a subtractor then A is called minuend and B as subtrahend.

30. Full subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
Explanation: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit, subtrahend bit and borrow from the previous stage. However, it also produces 2 outputs BORROW and DIFFERENCE.

31. The full subtractor can be implemented using ___________
a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate
Explanation: A full subtractor has 3 input bits and two outputs bits BORROW and DIFFERENCE. The full subtractor can be implemented using two half subtractors and an OR gate.

32. The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
Explanation: The difference output of a subtractor is given by (if A, B and X are the inputs) A XOR B XOR X.

33. The output of a full subtractor is same as ____________
c) Half subtractor
d) Decoder
Explanation: The sum and difference output of a full adder and a full subtractor are same. If A, B and C are the input of a full adder and a full subtractor then the output will be given by (A XOR B XOR C), respectively.

34. The decimal number system represents the decimal number in the form of ____________
b) Binary coded
c) Octal
d) Decimal
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Hexadecimal and Octal are number systems having base 16 and 8 respectively.

35. 29 input circuit will have total of ____________
a) 32 entries
b) 128 entries
c) 256 entries
d) 512 entries
Explanation: 29 input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.

36. BCD adder can be constructed with 3 IC packages each of ____________
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. BCD adder can be constructed with 3 IC packages. Each of 4-bit adders is an MSI(Medium scale Integration) function and 3 gates for the correction logic need one SSI (Small Scale Integration) package.

37. The output sum of two decimal digits can be represented in ____________
a) Gray Code
b) Excess-3
c) BCD
Explanation: The output sum of two decimal digits can be represented in BCD(Binary-coded decimal). Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight.

38. The addition of two decimal digits in BCD can be done through ____________
Explanation: The addition of two decimal digits in BCD can be done through BCD adder. Every input inserted, in addition by the user converted into binary and then proceed for the addition. Whereas, Full Adder, Ripple Carry Adder and Carry Look Adder are for the addition of binary bits.

39. 3 bits full adder contains ____________
a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
Explanation: 3 bits full adder contains 23 = 8 combinational inputs.

40. The simplified expression of full adder carry is ____________
a) c = xy+xz+yz
b) c = xy+xz
c) c = xy+yz
d) c = x+y+z
Explanation: A full adder is a combinational circuit having 3 inputs and 2 outputs, namely SUM and CARRY. The simplified expression of full adder carry is c = xy+xz+yz.

41. Complement of F’ gives back __________
a) F’
b) F
c) FF
d) FF’
Explanation: Complement means inversion. So, complement of F’ gives back F, as per the Law of Involution.

42. Decimal digit in BCD can be represented by ____________
a) 1 input line
b) 2 input lines
c) 3 input lines
d) 4 input lines
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Decimal digit in BCD can be represented by 4 input lines. Since it is constructed with 4-bits.

43. The number of logic gates and the way of their interconnections can be classified as ____________
a) Logical network
b) System network
c) Circuit network
d) Gate network
Explanation: The number of different levels of logic gates is represented in a fashion which is known as a logical network.

44. The word demultiplex means ___________
a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor
Explanation: The word demultiplex means “one into many” and distributor. A demultiplexer sends a single input to multiple outputs, depending on the select lines. It is clear from the diagram:

45. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For one input, the demultiplexer gives several outputs. That is why, it is called a data distributor.

46. Most demultiplexers facilitate which type of conversion?
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. Demultiplexer converts single input into multiple outputs.

47. In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
c) 4
d) 5
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. Therefore, for 1:4 demultiplexer, 2 select lines are required.

48. In a multiplexer the output depends on its ___________
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As the select input changes, the output of the multiplexer varies according to that input.

49. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be ___________
a) Y0
b) Y1
c) Y2
d) Y3
Explanation: It can be calculated from the figure shown below:

For C0 =1 and C1 =0, Y1 will be the output as 0 and 1 are the bit combinations of 1.

50. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ___________
a) Y0
b) Y1
c) Y2
d) Y3
Explanation: It can be calculated from the figure shown below:

For C0 =1 and C1 =0, Y3 will be the output as 0 and 1 are the bit combinations of 1.

51. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this case n = 3 since 23 = 8.

52. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
Explanation: The number of AND gates required will be equal to the number of outputs in a demultiplexer, which are 8.

53. The output Q4 of this 1-to-8 demultiplexer is ____________

a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
Explanation: The output Y4 = Q2.(Q1)’.(Q0)’.I. since the bit combinations of 4 are 100.

54. Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.

55. How many inputs will a decimal-to-BCD encoder have?
a) 4
b) 8
c) 10
d) 16
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. Thus, a Decimal-to-bcd converter has decimal values as inputs which range from 0-9. So, total 10 inputs are there in a decimal-to-BCD encoder.

56. How many outputs will a decimal-to-BCD encoder have?
a) 4
b) 8
c) 12
d) 16
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. Thus, a decimal to BCD encoder has 4 outputs.

57. How is an encoder different from a decoder?
a) The output of an encoder is a binary code for 1-of-N input
b) The output of a decoder is a binary code for 1-of-N input
c) The output of an encoder is a binary code for N-of-1 output
d) The output of a decoder is a binary code for N-of-1 output
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. It performs the opposite operation of a decoder which results in 2n outputs from n inputs. Thus, an encoder different from a decoder because of the output of an encoder is a binary code for 1-of-N input.

58. If we record any music in any recorder, such types of process is called ___________
a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
Explanation: If we record any music in any recorder, it means that we are giving data to a recorder. So, such process is called encoding. Getting back the music from the recorded data, is known as decoding.

59. Can an encoder be a transducer?
a) Yes
b) No
c) May or may not be
d) Both are not even related slightly
Explanation: Of course, a transducer is a device which has the capability to emit data as well as to accept. Transducer converts signal from one form of energy to another.

60. How many OR gates are required for a Decimal-to-bcd encoder?
a) 2
b) 10
c) 3
d) 4
Explanation: An encoder is a combinational circuit encoding the information of 2^n input lines to n output lines, thus producing the binary equivalent of the input.
This is clear from the diagram that it requires 4 OR gates:
.

61. How many OR gates are required for an octal-to-binary encoder?
a) 3
b) 2
c) 8
d) 10
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. Thus, in octal to binary encoder there are 8 (=23) inputs, thus 3 output lines.

62. For 8-bit input encoder how many combinations are possible?
a) 8
b) 2^8
c) 4
d) 2^4
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. There are 28 combinations are possible for an 8-bit input encoder but out of which only 8 are used using 3 output lines. It is a disadvantage of encoder.

63. The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is resolved by using additional input known as ___________
a) Enable
b) Disable
c) Strobe
d) Clock
Explanation: Such problems are resolved by using enable input, which behaves as active if it gets 0 as input since it is an active-low pin.

64. Can an encoder be called as multiplexer?
a) No
b) Yes
c) Sometimes
d) Never
Explanation: A multiplexer or MUX is a combination circuit that contains more than one input line, one output line and more than one selection line. Whereas, an encoder is also considered a type of multiplexer but without a single output line and without any selection lines.

65. If two inputs are active on a priority encoder, which will be coded on the output?
a) The higher value
b) The lower value
c) Neither of the inputs
d) Both of the inputs
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. If two inputs are active on a priority encoder, the input of higher value will be coded in the output.

#### Module 04

1. A latch is an example of a ___________
a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) 555 timer
Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is one in which the circuit is stable in either of two states. It can be flipped from one state to the other state and vice-versa.

2. Latch is a device with ___________
a) One stable state
b) Two stable state
c) Three stable state
d) Infinite stable states
Explanation: Since, a latch works on the principal of bistable multivibrator. A Bistable multivibrator is one in which the circuit is stable in either of two states. It can be flipped from one state to the other state and vice-versa. So a latch has two stable states.

3. Why latches are called a memory devices?
a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) It can store infinite amount of data
Explanation: Latches can be memory devices, and can store one bit of data for as long as the device is powered. Once device is turned off, the memory gets refreshed.

4. Two stable states of latches are ___________
a) Astable & Monostable
b) Low input & high output
c) High output & low output
d) Low output & high inputAnswer: c
Explanation: A latch has two stable states, following the principle of Bistable Multivibrator. There are two stable states of latches and these states are high-output and low-output.

5. How many types of latches are ___________
a) 4
b) 3
c) 2
d) 5
Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D latch is a modified form of SR latch whereas, T latch is an advanced form of JK latch.

6. The full form of SR is ___________
a) System rated
b) Set reset
d) Set Rated
Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.

7. The SR latch consists of ___________
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states.
The diagram of SR latch is shown below:

8. The outputs of SR latch are ___________
a) x and y
b) a and b
c) s and r
d) q and q’
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear from the diagram:
.

9. The NAND latch works when both inputs are ___________
a) 1
b) 0
c) Inverted
d) Don’t cares
Explanation: The NAND latch works when both inputs are 1. Since, both of the inputs are inverted in a NAND latch.

10. The first step of analysis procedure of SR latch is to ___________
a) label inputs
b) label outputs
c) label states
d) label tables
Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so because the flip flops have inverting gates inside them, hence in order to have both Q and Q complement available, we have atleast one output labelled.

11. The inputs of SR latch are ___________
a) x and y
b) a and b
c) s and r
d) j and k
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear from the diagram:

12. When a high is applied to the Set line of an SR latch, then ___________
a) Q output goes high
b) Q’ output goes high
c) Q output goes low
d) Both Q and Q’ go high
Explanation: S input of a SR latch is directly connected to the output Q. So, when a high is applied Q output goes high and Q’ low.

13. When both inputs of SR latches are low, the latch ___________
a) Q output goes high
b) Q’ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
Explanation: When both inputs of SR latches are low, the latch remains in it’s present state. There is no change in the output.

14. When both inputs of SR latches are high, the latch goes ___________
a) Unstable
b) Stable
c) Metastable
d) Bistable
Explanation: When both gates are identical and this is “metastable”, and the device will be in an undefined state for an indefinite period.

15. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are directly connected to the other’s output. Such types of structure is called cross coupling and due to which latches remain in the latched condition.

16. One example of the use of an S-R flip-flop is as ___________
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused during the switching of electronic devices.

17. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or Undefined State occurs at both S and R being at 1.

18. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set and Toggle.

19. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Explanation: In D flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid state at both inputs being 1.

20. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross coupling means the output of second gate is fed to the input of first gate and vice-versa.

21. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called sequential circuits. Unlike sequential circuits, if output depends only on the present state, then it’s known as combinational circuits.

22. Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Explanation: Combinational circuits are often faster than sequential circuits. Since, the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. Latches and Flip-flops come under sequential circuits.

23. How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock signal.
24. The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
Explanation: The sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information.

25. The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the second output Q’ = 1 and vice versa.

26. In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.

27. The output of latches will remain in set/reset untill ___________
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change the state.

28. What is a trigger pulse?
a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.

29. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
Explanation: The cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits. Moreover, they are referred to as asynchronous because they function in the absence of a clock pulse.

30. What is an ambiguous condition in a NAND based S’-R’ latch?
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and this condition is called as ambiguous/forbidden state. This state is also known as an Invalid state as the system goes into an unexpected situation.

31. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________
a) No change
b) Set
c) Reset
d) Forbidden
Explanation: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in the state. It remains in its prior state. This state is used for the storage of data.

32. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
a) A D latch at each of its input
b) An inverter at each of its input
c) It can never be converted
d) Both a D latch and an inverter at its input
Explanation: A NAND based S’-R’ latch can be converted into S-R latch by placing either a D latch or an inverter at its input as it’s operations will be complementary.

33. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is ____________
a) The inputs of NOR latch are 0 but 1 for NAND latch
b) The inputs of NOR latch are 1 but 0 for NAND latch
c) The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch
d) The output of NOR latch is 1 but 0 for NAND latch
Explanation: Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch are 0 but 1 for NAND latch.

34. The characteristic equation of S-R latch is ____________
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) = (S + Q(n))R’.

35. The difference between a flip-flop & latch is ____________
a) Both are same
b) Flip-flop consist of an extra output
c) Latches has one input but flip-flop has two
d) Latch has two inputs but flip-flop has one
Explanation: Flip-flop is a modified version of latch. To determine the changes in states, an additional control input is provided to the latch.

36. How many types of flip-flops are?
a) 2
b) 3
c) 4
d) 5
Explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an advanced version of S-R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.

37. The S-R flip flop consist of ____________
a) 4 AND gates
d) 3 AND gates
Explanation: The S-R flip flop consist of two additional AND gates at the S and R inputs of S-R latch.

38. What is one disadvantage of an S-R flip-flop?
a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State
Explanation: The main drawback of s-r flip flop is invalid output when both the inputs are high, which is referred to as Invalid State.

39. One example of the use of an S-R flip-flop is as ____________
a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator
Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is referred to as binary storage element. It functions as memory storage during the No Change State.

40. When is a flip-flop said to be transparent?
a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) When the Q output is complementary of the input
Explanation: Flip-flop have the property of responding immediately to the changes in its inputs. This property is called transparency.

41. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
Explanation: Edge triggered device will follow when there is transition. It is a positive edge triggered when transition takes place from low to high, while, it is negative edge triggered when the transition takes place from high to low.

42. What is the hold condition of a flip-flop?
a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active
Explanation: The hold condition in a flip-flop is obtained when both of the inputs are LOW. It is the No Change State or Memory Storage state if a flip-flop.

43. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________
a) SET
b) RESET
c) Clear
d) Invalid
Explanation: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no change. So, it remains in reset. If S=1, R=0, the flip flop is at the set condition.

44. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________
a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit
Explanation: The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the edge-detection circuit.

45. In D flip-flop, D stands for _____________
a) Distant
b) Data
c) Desired
d) Delay
Explanation: The D of D-flip-flop stands for “data”. It stores the value on the data line.

46. The D flip-flop has _______ input.
a) 1
b) 2
c) 3
d) 4
Explanation: The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the value on the data line.

47. The D flip-flop has ______ output/outputs.
a) 2
b) 3
c) 4
d) 1
Explanation: The D flip-flop has two outputs: Q and Q complement. The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the value on the data line.

48. A D flip-flop can be constructed from an ______ flip-flop.
a) S-R
b) J-K
c) T
d) S-K
Explanation: A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter between S and R and assigning the symbol D to the S input.

49. In D flip-flop, if clock input is LOW, the D input ___________
a) Has no effect
b) Goes high
c) Goes low
d) Has effect
Explanation: In D flip-flop, if clock input is LOW, the D input has no effect, since the set and reset inputs of the NAND flip-flop are kept HIGH.

50. In D flip-flop, if clock input is HIGH & D=1, then output is ___________
a) 0
b) 1
c) Forbidden
d) Toggle

Explanation: If clock input is HIGH & D=1, then output is 0. It can be observed from this diagram:

51. Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?
a) The logic level at the D input is transferred to Q on NGT of CLK
b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH
c) The Q output is ALWAYS identical to the D input when CLK = PGT
d) The Q output is ALWAYS identical to the D input
Explanation: By the truth table of D flip flop, we can observe that Q always depends on D. Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q.

52. Which of the following is correct for a gated D flip-flop?
a) The output toggles if one of the inputs is held HIGH
b) Only one of the inputs can be HIGH at a time
c) The output complement follows the input when enabled
d) Q output follows the input D when the enable is HIGH
Explanation: If clock is high then the D flip-flop operate and we know that input is equals to output in case of D flip-flop. It stores the value on the data line.

53. With regard to a D latch ________
a) The Q output follows the D input when EN is LOW
b) The Q output is opposite the D input when EN is LOW
c) The Q output follows the D input when EN is HIGH
d) The Q output is HIGH regardless of EN’s input state
Explanation: Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop output follows the input. It stores the value on the data line.

54. Which of the following is correct for a D latch?
a) The output toggles if one of the inputs is held HIGH
b) Q output follows the input D when the enable is HIGH
c) Only one of the inputs can be HIGH at a time
d) The output complement follows the input when enabled
Explanation: If the clock is HIGH then the D flip-flop operates and we know that input equals to output in case of D flip flop. It stores the value on the data line.

55. Which of the following describes the operation of a positive edge-triggered D flip-flop?
a) If both inputs are HIGH, the output will toggle
b) The output will follow the input on the leading edge of the clock
c) When both inputs are LOW, an invalid state exists
d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock
Explanation: Edge-triggered flip-flop means the device will change state during the rising or falling edge of the clock pulse. The main phenomenon of the D flip-flop is that the o/p will follow the i/p when the enable pin is HIGH.

56. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1
Explanation: PGT refers to Positive Going Transition and NGT refers to negative Going Transition. Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage output will be 1 and hence the stage will be changed.

57. A positive edge-triggered D flip-flop will store a 1 when ________
a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH
Explanation: A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and the clock transitions from LOW to HIGH. While a negative edge-triggered D flip-flop will store a 0 when the D input is HIGH and the clock transitions from HIGH to LOW.

58. Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
a) Due to its capability to receive data from flip-flop
b) Due to its capability to store data in flip-flop
c) Due to its capability to transfer the data into flip-flop
d) Due to erasing the data from the flip-flop
Explanation: Due to its capability to transfer the data into flip-flop. D-flip-flops stores the value on the data line.

59. The characteristic equation of D-flip-flop implies that ___________
a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state
Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of D flip-flop is given by Q(n+1) = D; which indicates that the next state is independent of the present state.

60. The characteristic equation of J-K flip-flop is ______________
a) Q(n+1)=JQ(n)+K’Q(n)
b) Q(n+1)=J’Q(n)+KQ'(n)
c) Q(n+1)=JQ'(n)+KQ(n)
d) Q(n+1)=JQ'(n)+K’Q(n)
Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ'(n)+K’Q(n).

61. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
Explanation: In J-K flip-flop, if both the inputs are same then it behaves like T flip-flop.

62. In J-K flip-flop, the function K=J is used to realize _____________
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
Explanation: T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.

63. The only difference between a combinational circuit and a flip-flop is that _____________
a) The flip-flop requires previous state
b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) The flip-flop depends on the past as well as present states
Explanation: Both flip-flop and latches are memory elements with clock/control inputs. They depend on the past as well as present states. Whereas, in case of combinational circuits, they only depend on the present state.

64. How many stable states a combinational circuits have?
a) 3
b) 4
c) 2
d) 5
Explanation: The two stable states of combinational circuits are 1 and 0. Whereas, in flip-flops there is an additional state known as Forbidden State.

65. The flip-flop is only activated by _____________
a) Positive edge trigger
b) Negative edge trigger
c) Either positive or Negative edge trigger
d) Sinusoidal trigger
Explanation: Flip flops can be activated with either a positive or negative edge trigger.

66. The S-R latch composed of NAND gates is called an active low circuit because _____________
a) It is only activated by a positive level trigger
b) It is only activated by a negative level trigger
c) It is only activated by either a positive or negative level trigger
d) It is only activated by sinusoidal trigger
Explanation: Active low indicates that only an input value of 0 sets or resets the circuit.

67. Both the J-K & the T flip-flop are derived from the basic _____________
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop
Explanation: The SR latch is the basic block for the D latch/flip flop from which the JK and T flip flops are derived. A latch is similar to a flip-flop, only without a clock input.

68. The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T
Explanation: Unlike the SR latch, these circuits have no invalid states. The SR latch or flip-flop has an invalid or forbidden state where no output could be determined.

69. What does the triangle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Edge triggered
c) Both Level enabled & Edge triggered
d) Level triggered
Explanation: The triangle on the clock input of a J-K flip-flop mean edge triggered. Whereas the absence of triangle symbol implies that the flip-flop is level-triggered.

70. What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered

Explanation: The circle on the clock input of a J-K flip-flop mean negative edge triggered. Whereas the absence of triangle symbol implies that the flip-flop is level-triggered.

71. What does the direct line on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
Explanation: The direct line on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.

72. What does the half circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
Explanation: The half circle on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.

73. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is _____________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave
Explanation: As one flip flop is used so there are two states available. So, 20/2 = 10Hz frequency is available at the output.

74. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
Explanation: Edge triggered device will follow the input condition when there is a transition. It is said to be positive edge triggered when transition occurs from LOW to HIGH. While it is said to be negative edge triggered when a transition occurs from HIGH to LOW.

75. How many natural states will there be in a 4-bit ripple counter?
a) 4
b) 8
c) 16
d) 32
Explanation: In an n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.

76. A ripple counter’s speed is limited by the propagation delay of _____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Explanation: A ripple counter is something that is derived by other flip-flops. It’s like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

77. One of the major drawbacks to the use of asynchronous counters is that ____________
a) Low-frequency applications are limited because of internal propagation delays
b) High-frequency applications are limited because of internal propagation delays
c) Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications
d) Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications
Explanation: One of the major drawbacks to the use of asynchronous counters is that High-frequency applications are limited because of internal propagation delays. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

78. Internal propagation delay of asynchronous counter is removed by ____________
a) Ripple counter
b) Ring counter
c) Modulus counter
d) Synchronous counter
Explanation: Propagation delay refers to the amount of time taken in producing an output when the input is altered. Internal propagation delay of asynchronous counter is removed by synchronous counter because clock input is given to each flip-flop individually in synchronous counter.

79. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
a) The output increases by 1
b) The output decreases by 1
c) The output word increases by 2
d) The output word decreases by 2
Explanation: In an asynchronous counter, there isn’t any clock input. The output of 1st flip-flop is given to second flip-flop as clock input. So, in case of binary down counter the output word decreases by 1.

78. How many flip-flops are required to construct a decade counter?
a) 4
b) 8
c) 5
d) 10
Explanation: Number of flip-flop required is calculated by this formula: 2(n-1) <= N< = 2n. 24=16and23=8, therefore, 4 flip flops needed.

79. The terminal count of a typical modulus-10 binary counter is ____________
a) 0000
b) 1010
c) 1001
d) 1111
Explanation: A binary counter counts or produces the equivalent binary number depending on the cycles of the clock input. Modulus-10 means count from 0 to 9. So, terminal count is 9 (1001).

80. How many different states does a 3-bit asynchronous counter have?
a) 2
b) 4
c) 8
d) 16
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.

81. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5 bits = 12ns * 5 = 60ns.

82. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?
a) 1
b) 2
c) 8
d) 15
Explanation: Transitional state is given by (2n – 1). Since, it’s a 4-bit counter, therefore, transition states = 24 – 1 = 15. So, total transitional states are 15.

83. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. One bit change is 15 ns, so 4-bit change = 15 * 4 = 60.

84. Three cascaded decade counters will divide the input frequency by ____________
a) 10
b) 20
c) 100
d) 1000

85. A ripple counter’s speed is limited by the propagation delay of ____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Explanation: A ripple counter is something that is derived by other flip-flops. Its like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

86. A 4-bit counter has a maximum modulus of ____________
a) 3
b) 6
c) 8
d) 16
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.

87. A principle regarding most display decoders is that when the correct input is present, the related output will switch ____________
a) HIGH
b) To high impedance
c) To an open
d) LOW
Explanation: A principle regarding most display decoders is that when the correct input is present, the related output will switch LOW. Since it’s an active-low device.

88. Which of the following statements are true?
a) Asynchronous events does not occur at the same time
b) Asynchronous events are controlled by a clock
c) Synchronous events does not need a clock to control them
d) Only asynchronous events need a control clock
Explanation: Asynchronous events does not occur at the same time because of propagation delay and they do need a clock pulse to trigger them. Whereas, synchronous events occur in presence of clock pulse.

89. A down counter using n-flip-flops count ______________
a) Downward from a maximum count
b) Upward from a minimum count
c) Downward from a minimum to maximum count
d) Toggles between Up and Down count
Explanation: As the name suggests down counter means counting occurs from a higher value to lower value (i.e. (2^n – 1) to 0).

90. UP Counter is ____________
a) It counts in upward manner
b) It count in down ward manner
c) It counts in both the direction
d) Toggles between Up and Down count
Explanation: UP counter counts in an upward manner from 0 to (2^n – 1).

91. DOWN counter is ____________
a) It counts in upward manner
b) It count in downward manner
c) It counts in both the direction
d) Toggles between Up and Down count
Explanation: DOWN counter counts in a downward manner from (2^n – 1) to 0.

92. How many different states does a 3-bit asynchronous down counter have?
a) 2
b) 4
c) 6
d) 8
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.

93. In a down counter, which flip-flop doesn’t toggle when the inverted output of the preceeding flip-flop goes from HIGH to LOW.
a) MSB flip-flop
b) LSB flip-flop
c) Master slave flip-flop
d) Latch
Explanation: Since, the LSB flip-flop changes its state at each negative transition of clock. That is why LSB flip-flop doesn’t have toggle.

94. In a 3-bit asynchronous down counter, the initial content is ____________
a) 000
b) 111
c) 010
d) 101
Explanation: Initially, all the flip-flops are RESET. So, the initial content is 000. At the first negative transition of the clock, the counter content becomes 101.

95. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes ____________
a) 000
b) 111
c) 101
d) 010
Explanation: Since, in the down counter, the counter content is decremented by 1 for every negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes 111.

96. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes ____________
a) 000
b) 111
c) 101
d) 010
Explanation: Since, in the down counter, the counter content is decremented by 1 for every negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes 101.

97. The hexadecimal equivalent of 15,536 is ________
a) 3CB0
b) 3C66
c) 63C0
d) 6300
Explanation: You just divide the number by 16 at the end and store the remainder from bottom to top.

98. In order to check the CLR function of a counter ____________
a) Apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
b) Ground the CLR input and check to be sure that all of the Q outputs are LOW
c) Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
d) Connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling
Explanation: CLR stands for clearing or resetting all states of flip-flop. In order to check the CLR function of a counter, apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state.

#### Module 05

1. Memory is a/an ___________
a) Device to collect data from other computer
b) Block of data to keep data separately
c) Indispensable part of computer
d) Device to connect through all over the world
Explanation: Memory is an indispensable unit of a computer and microprocessor based systems which stores permanent or temporary data.

2. The instruction used in a program for executing them is stored in the __________
a) CPU
b) Control Unit
c) Memory
d) Microprocessor
Explanation: All of the program and the instructions are stored in the memory. The processor fetches it as and when required.

3. A flip flop stores __________
a) 10 bit of information
b) 1 bit of information
c) 2 bit of information
d) 3-bit information
Explanation: A flip-flop has capability to store 1 bit of information. It can be used further after erasing previous information.

4. A register is able to hold __________
a) Data
b) Word
c) Nibble
d) Both data and word
Explanation: Register is also a part of memory inside a computer. It stands there to hold a word. A word is a group of 16-bits or 2-bytes.

5. A register file holds __________
a) A large number of word of information
b) A small number of word of information
c) A large number of programs
d) A modest number of words of information
Explanation: A register file is different from a simple register because of capability to hold a modest number of words of information. A word is a group of 16-bits or 2-bytes.

6. The very first computer memory consisted of __________
a) A small display
b) A large memory storage equipment
c) An automatic keyboard input
d) An automatic mouse input
Explanation: The very first computer memory consisted of a minute magnetic toroid, which required large, bulky circuit boards stored in large cabinates.

7. A minute magnetic toroid is also called as __________
a) Large memory
b) Small memory
c) Core memory
d) Both small and large memory
Explanation: A minute magnetic toroid is also called as core memory which is made up of a semiconductor. A semiconductor is a device whose electrical conductivity lies between that of conductor and insulator.

8. Which one of the following has capability to store data in extremely high densities?
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
Explanation: Semiconductor has capability to store data in extremely high densities.

9. A large memory is compressed into a small one by using __________
a) LSI semiconductor
b) VLSI semiconductor
c) CDR semiconductor
d) SSI semiconductor
Explanation: VLSI (Very Large Scale Integration) semiconductor is used in modern computers to short the size of memory.

10. VLSI chip utilizes __________
a) NMOS
b) CMOS
c) BJT
d) All of the Mentioned
Explanation: VLSI (Very Large Scale Integration) is a memory chip which is made up of NMOS, CMOS, BJT, and BiCMOS. It can include 10,000 to 100,000 gates per IC.

11. CD-ROM refers to __________
a) Floppy disk
d) Compressed Disk- Random Access Memory
Explanation: CD-ROM refers to Compact Disk-Read Only Memory.

12. Data stored in an electronic memory cell can be accessed at random and on demand using __________
d) Control Unit
Explanation: Direct addressing eliminates the need to process a large stream of irrelevant data in order to the desired data word.

13. The full form of PLD is __________
a) Programmable Large Device
b) Programmable Long Device
c) Programmable Logic Device
d) Programmable Lengthy Device
Explanation: The full form of PLD is Programmable Logic Device.

14. The evolution of PLD began with __________
a) EROM
b) RAM
c) PROM
d) EEPROM
Explanation: The evolution of PLD (Programmable Logic Device) began with Programmable Read Only Memory (i.e. PROM). Here, the ROM can be externally programmed as per the user.

15. A ROM is defined as __________
Explanation: A ROM is defined as Read Only Memory which can read the instruction stored in a computer.

16. Which of the following has the capability to store the information permanently?
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
Explanation: ROM (Read Only Memory) has the capability to store the information permanently. RAM provides random access to memory. Storage cells are responsible for the transfer of data from and into the memory.

17. ROM has the capability to perform _____________
a) Write operation only
c) Both write and read operation
d) Erase operation
Explanation: ROM means “Read Only Memory”. Hence, it has capability to perform read operation only. No write or erase operation could be performed in the ROM.

18. Since, ROM has the capability to read the information only then also it has been designed, why?
a) For controlling purpose
c) For booting purpose
d) For erasing purpose
Explanation: ROM means “Read Only Memory”. Hence, it has capability to perform read operation only. No write or erase operation could be performed in the ROM. It has designed to provide the computer with resident programmes and for booting purpose.

19. The ROM is a ___________
a) Sequential circuit
b) Combinational circuit
c) Magnetic circuit
d) Static circuit
Explanation: ROM is a combination of different ICs. So, it is a combinational circuit.
It depends on present input and not past states.

20. ROM is made up of ___________
a) NAND and OR gates
b) NOR and decoder
c) Decoder and OR gates
d) NAND and decoder
Explanation: ROM (Read Only Memory) has the capability to store the information permanently. ROM is made up of decoder and OR gates within a single IC package.

21. Why are ROMs called non-volatile memory?
a) They lose memory when power is removed
b) They do not lose memory when power is removed
c) They lose memory when power is supplied
d) They do not lose memory when power is supplied
Explanation: Volatile memory stores data as long as it is powered. ROMs are called non-volatile memory because of they do not lose memory when power is removed.

22. In ROM, each bit is a combination of the address variables is called ___________
a) Memory unit
b) Storage class
c) Data word
Explanation: In ROM, each bit combination that comes out of the output lines is called data word. Usually, a word consists of 16-bits or 2-bytes.

23. Which is not a removable drive?
a) Zip
b) Hard disk
c) Super Disk
d) Jaz
Explanation: Hard disk is present inside a computer. So, it is not a removable drive.

24. In ROM, each bit combination that comes out of the output lines is called ___________
a) Memory unit
b) Storage class
c) Data word
Explanation: In ROM, each bit combination that comes out of the output lines is called data word. Usually, a word consists of 16-bits or 2-bytes.

25. VLSI chip utilizes ___________
a) NMOS
b) CMOS
c) BJT
d) All of the Mentioned
Explanation: Very Large Scale Integration (VLSI) (ranging from 10,000 to 100,000 gates per IC) is a memory chip which is made up of NMOS, CMOS, BJT, and BiCMOS.

26. The time from the beginning of a read cycle to the end of tACS/tAA is called as ____________
a) Write enable time
b) Data hold
d) Access time
Explanation: The time from the beginning of a read cycle to the end of tACS/tAA is called as access time. It is the time in which data is fetched from the storage.

27. Why did PROM introduced?
a) To increase the storage capacity
b) To increase the address locations
c) To provide flexibility
d) To reduce the size
Explanation: In order to provide some flexibility in the possible applications of ROM, PROM is introduced. PROM stands for Programmable ROM, in which the ROM is programmed by the user.

28. Which of the following is programmed electrically by the user?
a) ROM
b) EPROM
c) PROM
d) EEPROM
Explanation: Programmable ROMs can be programmed electrically by the user but can’t be reprogrammed. EEPROMs can be electrically erased and re-programmed by the user.

29. PROMs are available in ___________
a) Bipolar and MOSFET technologies
b) MOSFET and FET technologies
c) FET and bipolar technologies
d) MOS and bipolar technologies
Explanation: PROMs (Programmable ROMs) can be programmed electrically by the user but can’t be reprogrammed. PROMs are available in both bipolar and MOS (Metal Oxide Semiconductor) technologies.

30. The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ___________
a) 4096
b) 16384
c) 32768
d) 8129
Explanation: 1 address can store 8 bits. Therefore, total capacity of a memory having n addresses = 8 * n.
total capacity of a memory = 2048 * 8 = 16384 bits.

31. How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?
a) Eight
b) Two
c) One
d) Four
Explanation: RAM stands for Random Access Memory in which any memory address can be accessed in any order. It requires word of length 8 bits. So, one word needs of 1 bit and 8 bit requires 8 bits.

32. Which of the following best describes the fusible-link PROM?
a) Manufacturer-programmable, reprogrammable
b) Manufacturer-programmable, one-time programmable
c) User-programmable, reprogrammable
d) User-programmable, one-time programmable
Explanation: The fusible-link PROM is user programmable and one time programmable. It means that a written program can not be reprogrammed. EPROMs can be erased and re-programmed.

33. How can ultraviolet erasable PROMs be recognized?
a) There is a small window on the chip
b) They will have a small violet dot next to the #1 pin
c) Their part number always starts with a “U”, such as in U12
d) They are not readily identifiable, since they must always be kept under a small cover
Explanation: An ultraviolet erasable PROMs have small window on the chip with black marked. Such type of PROMS are called EPROMS which are cleared by exposing it to UV radiation. They are re-programmable.

34. Which part of a Flash memory architecture manages all chip functions?
a) Program verify code
b) Floating-gate MOSFET
c) Command code
d) Input/Output pins
Explanation: MOSFET technology is the best one in the manufacturing of chip because it has high flexibility and storage capacity. Thus, Floating-Gate MOSFET part of a Flash Memory architecture manages all chip functions.

35. How much locations an 8-bit address code can select in memory?
a) 8 locations
b) 256 locations
c) 65,536 locations
d) 131,072 locations
Explanation: An 8 bit address code requires 32 memory locations and it can hold maximum upto 32 * 8 = 256 locations = 28.

36. What is a fusing process?
a) It is a process by which data is passed to the memory
b) It is a process by which data is read through the memory
c) It is a process by which programs are burnout to the diode/transistors
d) It is a process by which data is fetched through the memory
Explanation: Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

37. Fusing process is ___________
a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
Explanation: Since, any program cannot be reprogrammed in a PROM, so this process is irreversible as PROMs are programmed using the Fusing process. Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

38. The cell type used inside a PROM is ___________
b) Metal cells
c) Fuse cells
d) Electric cells
Explanation: The cell type used inside a PROM is fuse cells by which a program is burnout. Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

39. How many types of fuse technologies are used in PROMs?
a) 2
b) 3
c) 4
d) 5
Explanation: Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs. Three types of fuse technologies are used in PROMs and these are: (i) Metal links, (ii) Silicon links, & (iii) p-n junctions.

a) Polycrystalline
b) Magnesium sulfide
c) Nichrome
d) Silicon dioxide

a) Polycrystalline silicon
b) Polycrystalline magnesium
c) Nichrome
d) Silicon dioxide

42. During programming p-n junction is _____________
a) Avalanche reverse biased
b) Avalanche forward biased
c) Zener reverse biased
d) Zener reverse biased
Explanation: The sudden heavy flow of electrons in the reverse direction and heat cause aluminium ions to migrate. So, during programming p-n junction is avalanche reversed biased.

43. The full form of FAMOS is _____________
a) Floating Gate Avalanche Injection MOS
b) Float Gate Avalanche Injection MOS
c) Floating Gate Avalanche Induction MOS
d) Float Gate Avalanche Induction MOS
Explanation: The full form of FAMOS is Floating Gate Avalanche Injection MOS. It is a floating gate transistor in which the trapped electrons is responsible for the dropping of the voltage.

44. PROM is programmed by _____________
a) EPROM programmer
b) EEPROM programmer
c) PROM programmer
d) ROM programmer
Explanation: PROM is programmed by plugging it into a special device called PROM programmer. The ROM cannot be clear and hence PROM is a one-time programmable device.

45. The PROM starts out with _____________
a) 1s
b) 0s
c) Null
d) Both 1s and 0s
Explanation: PROM is a one-time programmable device, which is programmed by the user. The PROM starts out with all 0s. These current pulses blow the fuse links, thus creating the desire pattern.

46. For implementation of PROM, which IC is used?
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
Explanation: For implementation of PROM, IC 74186 is used. IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62 rows and 8 columns.

47. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
Explanation: IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62 rows and 8 columns.

a) 165,667
b) 245,784
c) 262,144
d) 212,342
Explanation: For n address bits, the memory location will consist of 2n bits. Using 18 address bits, 2^18 = 262,144 (= 256 K) words are addressed.

49. How many address bits are needed to operate a 2K * 8-bit memory?
a) 10
b) 11
c) 12
d) 13
Explanation: For n address bits, the memory location will consist of 2n bits. Thus, for 2K, only 11 address bits are required, because 211 = 2K.

50. What is the bit storage capacity of a ROM with a 1024 × 8 organization?
a) 1024
b) 4096
c) 2048
d) 8192
Explanation: For n address bits, the memory location will consist of 2n bits. 1024 = 210. So, 210 * 23 = 1024 * 8 = 8192 bit.

a) Polycrystalline silicon
b) Polycrystalline magnesium
c) Nichrome
d) Silicon dioxide

52. During programming p-n junction is _____________
a) Avalanche reverse biased
b) Avalanche forward biased
c) Zener reverse biased
d) Zener reverse biased
Explanation: The sudden heavy flow of electrons in the reverse direction and heat cause aluminium ions to migrate. So, during programming p-n junction is avalanche reversed biased.

53. The full form of FAMOS is _____________
a) Floating Gate Avalanche Injection MOS
b) Float Gate Avalanche Injection MOS
c) Floating Gate Avalanche Induction MOS
d) Float Gate Avalanche Induction MOS
Explanation: The full form of FAMOS is Floating Gate Avalanche Injection MOS. It is a floating gate transistor in which the trapped electrons is responsible for the dropping of the voltage.

54. PROM is programmed by _____________
a) EPROM programmer
b) EEPROM programmer
c) PROM programmer
d) ROM programmer
Explanation: PROM is programmed by plugging it into a special device called PROM programmer. The ROM cannot be clear and hence PROM is a one-time programmable device.

55. The PROM starts out with _____________
a) 1s
b) 0s
c) Null
d) Both 1s and 0s
Explanation: PROM is a one-time programmable device, which is programmed by the user. The PROM starts out with all 0s. These current pulses blow the fuse links, thus creating the desire pattern.

56. For implementation of PROM, which IC is used?
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
Explanation: For implementation of PROM, IC 74186 is used. IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62 rows and 8 columns.

57. IC 74186 is of ______________
a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
Explanation: IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62 rows and 8 columns.

a) 165,667
b) 245,784
c) 262,144
d) 212,342
Explanation: For n address bits, the memory location will consist of 2n bits. Using 18 address bits, 2^18 = 262,144 (= 256 K) words are addressed.

59. How many address bits are needed to operate a 2K * 8-bit memory?
a) 10
b) 11
c) 12
d) 13
Explanation: For n address bits, the memory location will consist of 2n bits. Thus, for 2K, only 11 address bits are required, because 211 = 2K.

60. What is the bit storage capacity of a ROM with a 1024 × 8 organization?
a) 1024
b) 4096
c) 2048
d) 8192
Explanation: For n address bits, the memory location will consist of 2n bits. 1024 = 210. So, 210 * 23 = 1024 * 8 = 8192 bit.

61. What is access time?
a) The time taken to move a stored word from one bit to other bits after applying the address bits
b) The time taken to write a word after applying the address bits
c) The time taken to read a stored word after applying the address bits
d) The time taken to erase a stored word after applying the address bits
Explanation: The access time is the time taken to read a stored word after applying the address bits in a MOS EPROM. It is the time required to fetch data from the memory.

62. What are the typical values of tOE?
a) 10 to 20 ns for bipolar
b) 25 to 100 ns for NMOS
c) 12 to 50 ns for CMOS
d) All of the Mentioned
Explanation: The access time is the time taken to read a stored word after applying the address bits in a MOS EPROM. It is the time required to fetch data from the memory. The typical values of tOE (i.e. access time) are 10 to 20 ns for bipolar, 25 to 100 ns for NMOS and 12 to 50 ns for CMOS.

63. Which of the following is not a type of memory?
a) RAM
b) FPROM
c) EEPROM
d) ROM
Explanation: EEPROM (Electrical Erasable Programmable ROM) is not a type of memory because it is used for erasing purpose only. Through EEPROM, data can be erased electrically, thereby consuming less time.

64. The chip by which both the operation of read and write is performed __________
a) RAM
b) ROM
c) PROM
d) EPROM
Explanation: A Random Access Memory (RAM) is a volatile chip memory in which both the read and write operations can be performed. Since it is volatile, therefore it stores data as long as power is on.

65. RAM is also known as __________
a) RWM
b) MBR
c) MAR
d) ROM
Explanation: A Random Access Memory (RAM) is a volatile chip memory in which both the read and write operations can be performed. Since it is volatile, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write Memory).

66. If a RAM chip has n address input lines then it can access memory locations upto __________
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write Memory). If a RAM chip has n address input lines then it can access memory locations upto 2n.

7. The n-bit address is placed in the __________
a) MBR
b) MAR
c) RAM
d) ROM
Explanation: The n-bit address is placed in the Memory Address Register (MAR) to select one of 2n memory locations. It stores the address of the instruction which is to be executed next.

68. Which of the following control signals are selected for read and write operations in a RAM?
a) Data buffer
b) Chip select
d) Memory
Explanation: Read and write are control signals that are used to enable memory for read and write operations respectively.

69. Computers invariably use RAM for __________
a) High complexity
b) High resolution
c) High speed main memory
d) High flexibility
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write Memory). Computers invariably use RAM for their high high-speed main memory and then use backup or slower-speed memories to hold auxiliary data.

70. How many types of RAMs are?
a) 2
b) 3
c) 4
d) 5
Explanation: There are two types of RAM and these are static and dynamic. Static RAM(SRAM) is faster than dynamic RAM(DRAM) as the access time for DRAM is more compared to that of SRAM.

71. Static RAM employs __________
a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
Explanation: Static RAM employs bipolar or MOS flip-flops because both the semiconductor has storing capacity. Thus, it’s access time is less and it is faster in operation.

72. Dynamic RAM employs __________
a) Capacitor or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
Explanation: Dynamic RAM employs a capacitor or MOSFET. Thus, it’s access time is more and it is slower in operation.

73. Which one of the following is volatile in nature?
a) ROM
b) EROM
c) PROM
d) RAM
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write Memory). RAMs are volatile because the stored data will be lost once the d.c. power applied to the flip-flops is removed.

74. The magnetic core memories have been replaced by semiconductor RAMs, why?
a) Semiconductor RAMs are highly flexible
b) Semiconductor RAMs have highest storing capacity
c) Semiconductor RAMs are smaller in size
d) All of the Mentioned
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is also known as RWM (i.e. Read Write Memory). The magnetic core memories have been replaced by semiconductor RAMs because of smaller in size, high storing capacity as well as flexibility.

75. The data written in flip-flop remains stored as long as __________
a) D.C. power is supplied
b) D.C. power is removed
c) A.C. power is supplied
d) A.C. power is removed
Explanation: Since flip-flops are made up of semiconductor materials. So, it can’t accept A.C. source and the data written in flip-flop remains stored as long as the dc power is maintained.

76. What is memory decoding?
a) The process of Memory IC used in a digital system is overloaded with data
b) The process of Memory IC used in a digital system is selected for the range of address assigned
c) The process of Memory IC used in a digital system is selected for the range of data assigned
d) The process of Memory IC used in a digital system is overloaded with data allocated in memory cell
Explanation: The Memory IC used in a digital system is selected or enabled only for the range of addresses assigned to it and this process is called memory decoding. It decodes the memory to be selected for a specific address.

77. The first step in the design of memory decoder is __________
a) Selection of a EPROM
b) Selection of a RAM
d) Data insertion
Explanation: Memory decoder decodes the memory to be selected for a specific address. The first step in the design of memory decoder is address assignment in non-overlapped manner.

78. How many address bits are required to select memory location in Memory decoder?
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB
Explanation: Memory decoder decodes the memory to be selected for a specific address. Since, the given EPROM and RAM are of 4 KB (4 * 1024 = 4096) capacity, it requires 12 address bit to select one of the 4096 memory locations.

79. How memory expansion is done?
a) By increasing the supply voltage of the Memory ICs
b) By decreasing the supply voltage of the Memory ICs
c) By connecting Memory ICs together
d) By separating Memory ICs
Explanation: Memory ICs can be connected together to expand the number of memory words or the number of bits per word.

80. IC 4116 is organised as _________
a) 512 * 4
b) 16 * 1
c) 32 * 4
d) 64 * 2
Explanation: IC 4116 is organised as 16 * 1 K which has capability to store 16 KB.

81. To construct 16K * 4-bit memory, how many 4116 ICs are required?
a) 1
b) 2
c) 3
d) 4
Explanation: Since, IC 4116 is organised as 16K * 1, which can store about 16KB data. So, four ICs are required for 16K * 4 memory implementation.

82. How many 1024 * 1 RAM chips are required to construct a 1024 * 8 memory system?
a) 4
b) 6
c) 8
d) 12
Explanation: One 1024 * 1 RAM chips is of 1-bit. SO, for construction of 1024 * 8 RAM chip of 8-bits, it will require 8 chips.

83. How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word length of 8 bits?
a) 2
b) 4
c) 6
d) 8
Explanation: 16K * 4 = 64K RAM is of 64K. Therefore, for a word of length 8-bits,
64 * 8 = 512K RAM required. Thus, number of 16K * 4 RAMs = 512/64 = 8.

84. The full form of PLD is _________
b) Programmable Logic Data
c) Programmable Logic Devices
Explanation: The full form of PLD is Programmable Logic Devices. It is a collection of gates, flip-flops and registers on a single chip.

85. PLD contains a large number of _________
a) Flip-flops
b) Gates
c) Registers
d) All of the Mentioned
Explanation: Programmable Logic Devices is a collection of a large number of gates, flip-flops, registers that are interconnected on the chip. Thus, it is used for designing logic circuits.

86. Logic circuits can also be designed using _________
a) RAM
b) ROM
c) PLD
d) PLA
Explanation: Programmable Logic Devices is a collection of large number of gates, flip-flops, registers that are interconnected on the chip. Thus, it is used for designing logic circuits.

87. In PLD, there are provisions to perform interconnections of the gates internally, because of _________
a) High reliability
b) High conductivity
c) The desired logic implementation
d) The desired output
Explanation: Programmable Logic Devices is a collection of a large number of gates, flip-flops, registers that are interconnected on the chip. In PLD, there are provisions to perform interconnections of the gates internally so that the desired logic can be implemented.

88. Why antifuses are implemented in a PLD?
a) To protect from high voltage
b) To increase the memory
c) To implement the programmes
d) As a switching devices
Explanation: Programmable Logic Devices is a collection of a large number of gates, flip-flops, registers that are interconnected on the chip. Programming is accomplished by using antifuses in a PLD and it is fabricated at the cross points of the gates.

89. How many types of PLD is?
a) 2
b) 3
c) 4
d) 5
Explanation: There are two types of PLD, viz., devices with fixed architecture and devices with a flexible architecture. The main categories of PLDs are PROM, PAL and PLA.

90. PLA refers to _________
b) Programmable Array Logic
c) Programmable Logic Array
d) Programmed Array Logic
Explanation: PLA refers to Programmable Logic Array. It is a type of PLD having programmable AND and OR gates.

#### Module 06

1. The correct syntax for using EXIT in a loop is ___________
a) EXIT loop_label WHEN condition;
b) EXIT WHEN condition loop_label;
c) loop_label WHEN condition EXIT
d) EXIT WHEN loop_label condition
Explanation: EXIT is the keyword used for the execution of EXIT statement. This keyword is followed by the optional loop label which again is followed by keyword WHEN and the condition which should by true for ending the loop. If the loop label is absent, then the exit statement automatically applies tot the innermost enclosing loop.

2. FOR loop uses a loop index, the type of loop index is _________
a) STD_LOGIC_VECTOR
b) BIT_VECTOR
c) INTEGER
d) REAL
Explanation: The loop index is used as a counter which counts the number of iterations and this loop index is an INTEGER by default. This is because by using an integer, the counting can be done easily which is not possible with real numbers.

3. Where do we declare the loop index of a FOR LOOP?
a) Entity
b) Architecture
c) Library
d) It doesn’t have to be declared
Explanation: The loop index doesn’t have to be declared because it is always an integer and can be directly used in a loop. So, it is locally declared for a loop. For example, FOR x in 1 TO 10 LOOP; Here ‘x’ is the loop index. Also, it can be reassigned a value within the loop.

4. A FOR loop is inside a WHILE loop. Inside the FOR loop, the EXIT statement is used in such a way that after 4 iterations, it will execute. After the execution of EXIT statement, the control will be passed ________
a) Outside the FOR loop
b) Outside the WHILE loop
c) At the next iteration of WHILE loop
d) At the next iteration of FOR loop
Explanation: If the loop is nested inside another loop, then exit statement will end the innermost loop only. It will not end the execution of all the loops. It will start execution from the innermost statement containing END LOOP. So, the control will be passed to the statement next to the end of FOR loop.

5. A for loop is initiated as given below, in total how many iterations will be there for the FOR loop?

`FOR i IN 0 TO 5 LOOP`

a) 3
b) 4
c) 5
d) 6
Explanation: As told earlier, i is the loop index which is integer by default. So, the counting will start from 0 and then 1 and so on till 5. Therefore, the loop will execute 6 times. If one wants to execute it 5 times then either 0 to 4 or 1 to 5 should be used.

6. All types of FOR loops are synthesizable.
a) True
b) False
Explanation: The loop index in FOR loop must contain a static value only. It is not possible to synthesize the design if the loop range is not static or it is a variable. So, we can’t use a variable in the loop range line otherwise the loop will not be synthesizable.

7. What is the use of EXIT statement in a loop?
a) For skipping one execution
b) For repeating one statement in the loop
c) For ending the condition and creating infinite loop
d) For ending the loop
Explanation: The exit statement completes the execution of an enclosing loop statement and passes the control to the statement after the exited loop. It will skip all the following iterations and starts execution after the statement containing END LOOP.

8. On what side of the assignment statement, one can use a loop index?
a) Left
b) Right
c) Left or Right
d) Loop index can’t be used in an assignment
Explanation: The loop index can be used on the right side of the assignment only. It has read only access. It means that we can’t use index as an output signal. However, it is possible to use this variable as an index to some vector type.

9. A WHILE loop is more flexible than FOR loop.
a) True
b) False
Explanation: Since we can’t use a signal or variable in the loop range statement, so the FOR loop always runs for a specified or constant number of times. Whereas a WHILE loop can be used to run a loop and we don’t need to know that how many times the loop must be executed.

10. The FOR loop is not synthesizable if it contains ______ statement.
a) WHEN
b) THEN
c) WAIT
d) IF
Explanation: The FOR loop is not synthesizable for two conditions. One is That the loop variable must be static. Another condition for the loop to be synthesizable is that it must not contain any kind of WAIT statement.

11. A combinational process must have all the _________ signals in its sensitivity list.
a.Used
b.Input

12. Which of the following VHDL design units contain the description of the circuit?

13. An entity can have more than one architecture.

14. In a VHDL program, the architecture can have more than one entity.

15. Which of the following describes the structure of a VHDL code correctly?

16. Multiple processes in a VHDL code are executed ______.

17. Which of the following constitute the contents of a sensitivity list?

18. _______ is the process of converting design information to a set of logic equations using EDA tools.

19. A common error with programming flip-flops is accidentally making a _______.

20. Which of the following represents the correct order?
a) Given function, optimized function, implementation
b) Optimized function, implementation, given function
c) Implementation, optimized function, given function
d) Given function, implementation, optimized function
Explanation: First of all we are given with a logic function that is first optimized before implementing it. The optimization is first done by using a suitable method and then it is implemented in the VHDL.

21. Which of the following will reduce the cost of implementation?
a) Implementing with only one modeling style
b) Implementing with dataflow modeling
c) Optimization
d) Generating Net list first
Explanation: Optimization is the technique to get the minimal form for a given logic function. By implementing this minimal function, the cost of implementation is reduced significantly.

22. Which of the following is not a method of optimization of logic function?
a) Tabular method
b) By using Boolean laws
c) K-map
d) Rectangular method
Explanation: There are various methods available for optimization of logic functions like K-map, Boolean reduction, tabular method and cubical method. There is no such method called rectangular method to optimize the logic function.

23. Which of the following k-map represents the following given function?

`y = AB + AB’C + A’BC`

a)
b)
c)
d)
Explanation: In the logic function there are three terms, AB’C representing 101 and A’BC representing 011. Third term is AB which will corresponds to two 1’s which are ABC and ABC’ corresponding to 111 and 110.

24. Which of the following is equivalent to the Boolean expression A + AB?
a) A
b) B
c) AB
d) A + B
Explanation: This expression can bide minimized by using simple Boolean laws. In the given expression, let us take A common. This becomes A (1 + B), According to sum laws of Boolean expressions, 1 + B must be equal to 1. So, it becomes A.1 which is equivalent to A.

25. Which of the following assignment statement is not generally used in the implementation of Boolean functions?
a) Concurrent assignment
b) Sequential assignment
c) Conditional assignment
d) Selected assignment
Explanation: Generally, these kind of optimized Boolean function doesn’t need any sequential processing and therefore, no sequential assignment is required. All the functions can be implemented with concurrent code only.

26. Which of the following are prime implicants of the following Boolean function?

`Y= AB + BC'D’ + BCD'`

a) A, B, C, D
b) AB, BC’D’, BCD’
c) AB, BD’
d) AB, CD
Explanation: Prime implicants of a function are the terms in the given function without any minimization. In this case the prime implicants are AB, BC’D’, BCD’.

27. How many logical operations are required to implement a Boolean function XY + X?
a) 0
b) 1
c) 2
d) 3
Explanation: The given function XY + X is first optimized to reduce the cost of implementation. So, the optimized function will be equal to X. As XY + X = X (Y + 1) = X. To implement this no logical operation is needed. It just needs an assignment statement and no operation.

28. Look the code given below. Which of the following option is implemented by the VHDL code?

```ARCHITECTURE my_func OF my_logic IS
BEGIN
y <= a AND (b XNOR c);```

END my_func;
a) B’C’ + BC
b) AB’ + A’B
c) AB’C’
d) ABC + AB’C’
Explanation: The given function is a AND (b XNOR c). So, It is Y = A.(B EXNOR C) = AB’C’ + ABC. So, option ABC + AB’C’ is the correct function which is implemented by the code.

29. What is the VHDL code for the logical function AB’C + ABC + BC?
a)

```   ARCHITECTURE my_logic OF my_logic IS
BEGIN
y <= (a AND b AND c) AND (b AND c);
END ARCHITECTURE;```

b)

```   ARCHITECTURE my_logic OF my_logic IS
BEGIN
y <= (a AND c) OR (b AND c);
END ARCHITECTURE;```

c)

```   ARCHITECTURE my_logic OF my_logic IS
BEGIN
y <= (a AND c) AND (b OR c);
END ARCHITECTURE;```

d)

```   ARCHITECTURE my_logic OF my_logic IS
BEGIN
y <= (a AND b AND c) OR (b AND c);
END ARCHITECTURE;```

Explanation: As per the process the function will be implemented after optimization. To optimize the function, AB’C + ABC + BC = AC(B + B’) + BC = AC + BC. So, the correct statement should be A AND C OR B AND C.

30. The ring counter is a serial shift register with feedback from the output of the last flip-flop to the input of the first flip-flop.
a) True
b) False
Explanation: Ring counter is a serial shift register based on continuous circulation. Feeding back the output of the serial shift register to its input without inversion creates a circuit.

31. Which of the following flip-flop is used by the ring counter?
a) D flip-flops
b) SR flip-flops
c) JK flip-flops
d) T flip-flops
Explanation: Ring counter comprises of a few single bit D flip-flops, one flip-flop for one data bit, either a logic 1 or a 0. They are connected together to form a sequence so that the output from the first flip-flop becomes the input of the second flip-flop and so on.

32. ‘shift_reg’ is used to initialize the _____________ in the shift register.
a) LSB
b) MSB
c) Register type
d) Register bits
Explanation: Shift register uses ‘shift_reg’ for the initialization. It sets the value of MSB in the shift register with the following code:
(signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := X”80″;)

33. How many types of shift operators are there in VHDL?
a) Three
b) Four
c) Five
d) Six
Explanation: There are six types of shift operators in VHDL: rol (rotate left logical), ror (rotate right logical), sll (shift left logical), srl (shift right logical), sla (shift left arithmetic), sra (shift right arithmetic).

34. How many types of the data type are there in the ring counter?
a) One
b) Two
c) Three
d) More than three
Explanation: There are more than three data types in VHDL, some of them are: STD_LOGIC_VECTOR data type – for more than one bit, the STD_LOGIC data type – for a single bit, the BIT_VECTOR data type – for two or more bits, STD_LOGIC_UNSIGNED data type – for addition and subtraction.

35. In __________ counter universal clock is not used.
a) Synchronous counter
b) Asynchronous counter
d) Ring counter
Explanation: In asynchronous counter, the universal clock is not used, only the first flip-flop is operated by the main clock and output of the previous flip-flops operates the clock input of the rest of the counters.

36. Synchronous counter use ________ global clock, unlike asynchronous counter.
a) One
b) Two
c) Three
d) zero
Explanation: Synchronous counter use one global clock that operates each flip flop and changes the output in parallel. One advantage of the synchronous counter as compared to asynchronous counter is, it can work on a much higher frequency than the asynchronous counter.

37. Asynchronous counters are generally used in circuits with higher frequency, where a large number of bits are involved.
a) True
b) False
Explanation: In asynchronous counters, there are small delays between the arrival of the clock pulse at the input due to the internal circuit of the gate so, if the delay of the all the stages are added together the total delay at the end of the counter can be very large. Therefore, asynchronous counters are not used in high-frequency circuits where large numbers of bits are involved.

38. How many different states does a decade counter count?
a) Eight
b) Nine
c) Ten
d) Eleven
Explanation: Ten different states are counted by a decade counter. It then resets to its initial state. A simple decade counter counts from 0 to 9. Also, counters could be made which can go through any ten states between 0 to 15.

39. The number of flip-flops used in a counter is _________ number of states in the counter.
a) Greater than
b) Less than
c) Equal to
d) Greater than equal to
Explanation: Number of flip-flops used in a counter is greater than equal to the number of states in the counter. It can be calculated by using ‘log2 n’ where n=number of states in the counter.

40. Two decade counters cascaded together will divide the input frequency by ________
a) 10
b) 100
c) 1000
d) 10000