1. 8086 Microprocessor supports _______ modes of operation.
A. 2
B. 3
C. 4
D. 5
Answer : A
Explanation: It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor.

2. Which of the following is not a Features of 8086?
A. It uses two stages of pipelining
B. It is available in 3 versions based on the frequency of operation
C. Fetch stage can prefetch up to 6 bytes of instructions
D. It has 512 vectored interrupts.
Answer : D
Explanation: It has 256 vectored interrupts is true Features of 8086.

3. 8086 can access up to?
A. 512KB
B. 1Mb
C. 2Mb
D. 256KB
Answer: B
Explanation: 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.

4. 8086 has ___ address bus.
A. 16-bit
B. 18-bit
C. 20-bit
D. 24-bit
Answer : C
Explanation: Address Bus : 8085 has 16-bit address bus while 8086 has 20-bit address bus.

5. Which flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0?
A. Binary bit
B. Zero flag
C. Sign flag
D. Overflow flag
Answer : B
Explanation: Zero flag : This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.

6. Which flag represents the result when the system capacity is exceeded?
A. Carry flag
B. Auxiliary flag
C. Trap flag
D. Overflow flag
Answer : D
Explanation: Overflow flag : This flag represents the result when the system capacity is exceeded.

7. It is an edge triggered input, which causes an interrupt request to the microprocessor.
A. NMA
B. INTR
C. INTA
D. ALE
Answer : A
Explanation: NMI : It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which causes an interrupt request to the microprocessor.

8. It is used to write the data into the memory or the output device depending on the status of M/IO signal.
A. IR
B. HLDA
C. HR
D. WR
Answer : D
Explanation: WR : It stands for write signal and is available at pin 29. It is used to write the data into the memory or the output device depending on the status of M/IO signal.

9. Which instruction is Used to load the address of operand into the provided register?
A. LEA
B. LDS
C. LES
D. LAHF
Answer : A
Explanation: LEA : Used to load the address of operand into the provided register.

10. The different ways in which a source operand is denoted in an instruction is known as
A. Instruction Set
B. Interrupts
C. 8086 Configuration
D. Addressing Modes
Answer : D
Explanation: The different ways in which a source operand is denoted in an instruction is known as addressing modes. There are 8 different addressing modes in 8086 programming

11. The remaining address line of ______ bus is decoded to generate chip select signal
A. Data
B. Address
C. Control bus
D. Both (a) and (b)
Answer : B

12. _______ signal is generated by combining RD and WR signals with IO/M
A. Control
B.  Memory
C. Register
D. System
Answer : A

13. Memory is an integral part of a _______ system
A. Supercomputer
B. Microcomputer
C. Mini computer
D. Mainframe computer
Answer : B

14. _____ has certain signal requirements write into and read from its registers
A. Memory
B. Register
C. Both (a) and (b)
D. Control
Answer : A

15. An _________ is used to fetch one address
A. Internal decoder
B. External decoder
C. Encoder
D. Register
Answer : A

16. The primary function of the _____________ is to accept data from I/P devices
A. Multiprocessor
B. microprocessor
C. Peripherals
D. Interfaces
Answer : B

17. ___________ signal prevent the microprocessor from reading the same data more than one
A. pipelining
B. Handshaking
C.  Controlling
D. Signaling
Answer : B

18. Bits in IRR interrupt are ______
A. Reset
B. Set
C. Stop
D. Start
Answer : B

19. __________ generate interrupt signal to microprocessor and receive acknowledge
A. Priority resolver
B. Control logic
C. Interrupt request register
D. Interrupt register
Answer : B

20. The _______ pin is used to select direct command word
A. A0
B. D7-D6
C. A12
D. AD7-AD6
Answer : A

21. 8086 Microprocessor supports _______ modes of operation.
A. 2
B. 3
C. 4
D. 5
Answer : A
Explanation: It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor.

22. Which of the following is not a Features of 8086?
A. It uses two stages of pipelining
B. It is available in 3 versions based on the frequency of operation
C. Fetch stage can prefetch up to 6 bytes of instructions
D. It has 512 vectored interrupts.
Answer: D
Explanation: It has 256 vectored interrupts is true Features of 8086.

23. 8086 can access up to?
A. 512KB
B. 1Mb
C. 2Mb
D. 256KB
Answer: B
Explanation: 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.

24. 8086 has ___ address bus.
A. 16-bit
B. 18-bit
C. 20-bit
D. 24-bit
Answer: C
Explanation: Address Bus : 8085 has 16-bit address bus while 8086 has 20-bit address bus.

25. Which flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0?
A. Binary bit
B. Zero flag
C. Sign flag
D. Overflow flag
Answer: B
Explanation: Zero flag : This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.

26. Which flag represents the result when the system capacity is exceeded?
A. Carry flag
B. Auxiliary flag
C. Trap flag
D. Overflow flag
Answer : D
Explanation: Overflow flag : This flag represents the result when the system capacity is exceeded.

27. It is an edge triggered input, which causes an interrupt request to the microprocessor.
A. NMA
B. INTR
C. INTA
D. ALE
Answer : A
Explanation: NMI : It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which causes an interrupt request to the microprocessor.

28. It is used to write the data into the memory or the output device depending on the status of M/IO signal.
A. IR
B. HLDA
C. HR
D. WR
Answer: D
Explanation: WR : It stands for write signal and is available at pin 29. It is used to write the data into the memory or the output device depending on the status of M/IO signal.

29. Which instruction is Used to load the address of operand into the provided register?
A. LEA
B. LDS
C. LES
D. LAHF
Answer: A
Explanation: LEA : Used to load the address of operand into the provided register.

30. The different ways in which a source operand is denoted in an instruction is known as
A. Instruction Set
B. Interrupts
C. 8086 Configuration
D. Addressing Modes
Answer: D
Explanation: The different ways in which a source operand is denoted in an instruction is known as addressing modes. There are 8 different addressing modes in 8086 programming

31. IP stand for
A. Industry pointer
B. Instruction pointer
C. Index pointer
D. None of these
Answer : B

32. Which has great important in modular programming
A. Stack segment
B. Queue segment
C. Array segment
D. All of these
Answer : A

33. Which register containing the 8086/8088 flag
A. Status register
B. Stack register
C. Flag register
D. Stand register
Answer :A

34. How many bits the instruction pointer is wide
A. 16 bit
B. 32 bit
C. 64 bit
D. 128 bit
Answer :A

35. How many type of addressing in memory
A. Logical address
B. Physical address
C. Both A and B
D. None of these
Answer : C

36. The size of each segment in 8086 is
A. 64 kb
B. 24 kb
C. 50 kb
D. 16kb
Answer :A

37. The physical address of memory is
A.20 bit
B. 16 bit
C. 32 bit
D. 64 bit
Answer :A

38. The _______ address of a memory is a 20 bit address for the 8086 microprocessor
A. Physical
B. Logical
C. Both
D. None of these
Answer :A

39. The pin configuration of 8086 is available in the________
A. 40 pin
B. 50 pin
C. 30 pin
D. 20 pin
Answer : A

40. DIP stand for
A. Deal inline package
B. Dual inline package
C. Direct inline package
D. Digital inline package
Answer :B

41.If MN/MX is low, the 8086 operates in _____ mode.
A. Minimum mode
B. Maximum mode
C. Both A and B
D. Control mode
Answer: B
Explanation: If MN/MX’ is tied to Ground, the 8086 operates in maximum mode and MN/MX’ is tied
to Vcc, the processor 8086 operates in minimum mode

42Which of the following processor supports pipelined architecture?
A. 8080
B. 8085
C. 8086
D. 8008
Answer: C
Explanation: 8086 microprocessor supports pipelined architecture because of its
predecoded instruction byte queue; it can fetch the next instruction while executing the
current instruction.

1. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative
Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears in the form of successive byte or bytes.

2. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
Answer: c
Explanation: Since immediate data is present in the instruction.

3. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
Answer: b
Explanation: Since the address is directly specified in the instruction as a part of it.

4. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
Answer: b
Explanation: Since register is used to refer the address.

5. The instruction, MOV AX,[BX] is an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
Answer: d
Explanation: Since the register used to refer to the address is accessed indirectly.

6. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
Answer: c
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest of them, address is stored.

7. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the content of a register or a memory location.

8. If the location to which the control is to be transferred lies in a different segment other than the current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a different segment.

9. The instruction, JMP 5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
Answer: c
Explanation: Since in intersegment direct mode, the address to which the control is to be transferred is in a different segment.

10. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
Answer: d
Explanation: The effective address is formed by adding the contents of both base and index registers to a default segment.

11. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned
Answer: c
Explanation: Machine language instruction format has one or more fields. The first one is the operation code field.

22. A machine language instruction format consists of
a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned
Answer: c
Explanation: Machine language instruction format has both the fields.

23. The length of the one-byte instruction is
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Answer: b
Explanation: This format is only one byte long.

24. The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Answer: a
Explanation: This format is 2 bytes long.

25. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
Answer: d
Explanation: The LSBs(least significant bits) from 0 to 3 represent R/M field that specifies another register or memory location i.e. the other operand.

26. In a machine instruction format, S-bit is the
a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned
Answer: c
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of operation.

27. The bit which is used by the ‘REP’ instruction is
a) W-bit
b) S-bit
c) V-bit
d) Z-bit
Answer: d
Explanation: The Z-bit is used by the REP instruction to control the loop.

28. If a W-bit value is ‘1’ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
Answer: c
Explanation: If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is of 8-bits.

29. The instructions which after execution transfer control to the next instruction in the sequence are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned
Answer: a
Explanation: The sequential control flow instructions follow sequence order in their execution.

30. The instructions that transfer the control to some predefined address or the address specified in the instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned
Answer: b
Explanation: The control transfer instructions transfer control to the specified address.

31. The instruction “JUMP” belongs to
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions
Answer: d
Explanation: The JUMP instruction transfers the control to the address located in the instruction.

32. The instruction, “INC” increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3
Answer: c
Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.

33. The instruction that subtracts 1 from the contents of the specified register/memory location is
a) INC
b) SUBB
c) SUB
d) DEC
Answer: d
Explanation: The DEC instruction decrements the contents of a specified register/memory location by 1.

34. The instruction that enables subtraction with borrow is
a) DEC
b) SUB
c) SBB
d) None of the mentioned
Answer: c
Explanation: The SBB instruction subtracts the source operand and the borrow flag from the destination operand.

35. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag
Answer: b
Explanation: If borrow exists in the subtraction operation performed then carry flag is set.

36. In general, the source operand of an instruction can be
a) memory location
b) register
c) immediate data
d) all of the mentioned
Answer: d
Explanation: The source operand is the element which is data or data stored memory location on which operation is performed.

37. In general, the destination operand of an instruction can be
a) memory location
b) register
c) immediate data
d) memory location and register
Answer: d
Explanation: Since the destination should be able to store the data, immediate data cannot be considered as a destination operand.

38. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication
Answer: b
Explanation: For comparison, the instruction CMP subtracts source operand from destination operand.

39. During comparison operation, the result of comparing or subtraction is stored in
a) memory
b) registers
c) stack
d) no where
Answer: d
Explanation: The result of subtraction operation is not stored anywhere during a comparison.

40. The instruction that converts the result in an unpacked decimal digits is
a) AAA
b) AAS
c) AAM
d) All of the mentioned
Answer: d
Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are called as “Unpacked BCD arithmetic instructions”.

41. Which of the following is a mnemonic?
a) ADD
b) ADC
c) AAA
d) ADD & ADC
Answer: c
Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.

42. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before dividing the two unpacked BCD digits.

43. The expansion of DAA is
a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary
Answer: c
Explanation: This instruction performs conversion operation.

44. The instruction that is used to convert the result of the addition of two packed BCD numbers to a valid BCD number is
a) DAA
b) DAS
c) AAA
d) AAS
Answer: a
Explanation: In this conversion, the result has to be only in AL.

45. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
c) left and then right
d) right and then left
Answer: b
Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.

46. The mnemonic that is placed before the arithmetic operation is performed is
a) AAA
b) AAS
c) AAM
d) AAD
Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL.

47. The Carry flag is undefined after performing the operation
a) AAA
b) ADC
c) AAM
d) AAD
Answer: d
Explanation: Since the operation, AAD is performed before division operation is performed, the carry flag, auxiliary flag and overflow flag are undefined.

48. The instruction that performs logical AND operation and the result of the operation is not available is
a) AAA
b) AND
c) TEST
d) XOR
Answer: c
Explanation: In the TEST instruction, the logical AND operation is performed and the result is not stored but flags are affected.

49. In the RCL instruction, the contents of the destination operand undergo function as
a) carry flag is pushed into LSB & MSB is pushed into the carry flag
b) carry flag is pushed into MSB & LSB is pushed into the carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag
d) parity flag is pushed into MSB & LSB is pushed into the carry flag
Answer: a
Explanation: In RCL(Rotate right through carry), for each operation, the carry flag is pushed into LSB and the MSB of the operand is pushed into carry flag.

50. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS
Answer: b
Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX register becomes zero. When CX becomes zero, the execution proceeds to the next instruction in sequence.

51. Match the following

A) MOvSB/SW       1) loads AL/AX register by content of a string
B) CMPS           2) moves a string of bytes stored in source to destination
C) SCAS           3) compares two strings of bytes or words whose length is stored in CX register
D) LODS           4) scans a string of bytes or words

a) A-3,B-4,C-2,D-1
b) A-2,B-1,C-4,D-3
c) A-2,B-3,C-1,D-4
d) A-2,B-3,C-4,D-1
Answer: d
Explanation: By using the string instructions, the operations on strings can be performed.

52. The instructions that are used to call a subroutine from the main program and return to the main program after execution of called function are
a) CALL, JMP
b) JMP, IRET
c) CALL, RET
d) JMP, RET
Answer: c
Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the stack, before the control is transferred to the procedure. At the end of the procedure, the RET instruction must be executed to retrieve the stored contents of IP & CS registers from a stack.

53. The instruction that unconditionally transfers the control of execution to the specified address is
a) CALL
b) JMP
c) RET
d) IRET
Answer: b
Explanation: In this the control transfers to the address specified in the instruction and flags are not affected by this instruction.

54. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold
Answer: d
Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of the ‘halt’ state.

55. NOP instruction introduces
a) Address
b) Delay
c) Memory location
d) None of the mentioned
Answer: b
Explanation: NOP is the No operation. It means that the processor performs no operation for the clock cycle and thus there exists a delay.

56. Which of the following is not a machine controlled instruction?
a) HLT
b) CLC
c) LOCK
d) ESC
Answer: b
Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry Flag.

57. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned
Answer: d
Explanation: The machine level programming is complicated.

58. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains the coded object modules of the program to be assembled.

59. The advantages of assembly level programming are
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned
Answer: d
Explanation: The assembly level programming is more advantageous than the machine level programming.

60. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM
Answer: c
Explanation: All the files should have the extension, .ASM.

61. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
d) All of the mentioned
Answer: d
Explanation: Before starting the process of entering a small program on PC, ensure that all the files namely Norton’s editor, assembler, linker and debugger are available in the same directory in which work is been done.

62. The listing file is identified by
a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST
Answer: d
Explanation: The listing file is automatically generated in the assembly process and is identified by the entered or source file name and an extension .LST.

63. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
Answer: a
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid object file.

64. The listing file contains
a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned
Answer: d
Explanation: The listing file contains total offset map of source file including labels, offset addresses, opcodes, memory allotments for different directives and labels and relocation information.

65. DEBUG.COM facilitates the
a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
Answer: c
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.

66. DEBUG is able to troubleshoot only
a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
Answer: a
Explanation: The DEBUG may be used either to debug a source program or to observe the results of execution of an .EXE file.

1. The stack pointer register contains
a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment
Answer: c
Explanation: The stack pointer register contains the offset of the address of the stack segment.

2. The stack segment register contains
a) address of the stack segment
b) base address of the stack segment
c) pointer address of the stack segment
d) data in the stack segment
Answer: b
Explanation: The stack segment register contains base address of the stack segment in the memory. The stack pointer register (sP) and stack segment register (SS) together address the stack-top.

3. PUSH operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Answer: a
Explanation: Each PUSH operation decrements the SP ( Stack Pointer) register.

4. POP operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Answer: b
Explanation: Each POP operation increments the SP ( Stack Pointer) register.

5. The register or memory location that is pushed into the stack at the end must be
a) popped off last
b) pushed off first
c) popped off first
d) pushed off last
Answer: c
Explanation: The data can be retrieved by POP operation and as in stack, the data that is pushed at the end must be popped off first.

6. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK
the ASSUME directive directs to the assembler the
a) address of the stack segment
b) pointer address of the stack segment
c) name of the stack segment
d) name of the stack, code and data segments
Answer: d
Explanation: The directive ASSUME facilitates to name the segments with the desired name that is not a mnemonic or keyword.

7. When a stack segment is initialised then
a) SS and SP are initialised
b) only SS is initialised
c) only SP is initialised
d) SS and SP need not be initialised
Answer: a
Explanation: Though the Stack segment is initialised, the SS and SP pointers must be initialised.

8. The number of PUSH instructions and POP instructions in a subroutine must be
a) PUSH instructions must be greater than POP instructions
b) POP instructions must be greater than PUSH instructions
c) Both must be equal
d) Instructions may be any kind
Answer: c
Explanation: The number of PUSH instructions must be equal to the number of POP instructions.

9. 8086 does not support
a) Arithmetic operations
b) logical operations
c) BCD operations
d) Direct BCD packed multiplication
Answer: d
Explanation: The 8086 microprocessor does not support direct BCD packed operations.

10. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
a) 32K bytes
b) 64K bytes
c) 16K bytes
d) NONE
Answer: b
Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K bytes.

11. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
Answer: c
Explanation: An interrupt function is to break the sequence of operation.

12. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
Answer: a
Explanation: An interrupt transfers the control to interrupt service routine (ISR). After executing ISR, the control is transferred back again to the main program.

13. While executing the main program, if two or more interrupts occur, then the sequence of appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
Answer: d
Explanation: If an interrupt occurs while executing a program, and the processor is executing the interrupt, if one more interrupt occurs again, then it is called a nested interrupt.

14. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
Answer: c
Explanation: The processor if handles more devices as interrupts then it has multiple interrupt processing ability.

15. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
Answer: a
Explanation: NMI is the acronym for nonmaskable interrupt.

16. If any interrupt request given to an input pin cannot be disabled by any means then the input pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none of the mentioned
Answer: b
Explanation: A nonmaskable interrupt input pin is one which means that any interrupt request at NMI (nonmaskable interrupt) input cannot be masked or disabled by any means.

17. The INTR interrupt may be
a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned
Answer: a
Explanation: the INTR (interrupt request) is maskable or can be disabled.

18. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
Answer: b
Explanation: If more than one interrupt request (INTR) occurs at a time, then an external chip called programmable interrupt controller is required to handle them.

19. The INTR interrupt may be masked using the flag
a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
Answer: c
Explanation: If a microprocessor wants to serve any interrupt then interrupt flag, IF=1. If interrupt flag, IF=0, then the processor ignores the service.

20. The interrupt for which the processor has the highest priority among all the external interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Answer: c
Explanation: The Non-Maskable Interrupt input pin has the highest priority among all the external interrupts.

21. The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Answer: b
Explanation: TRAP is the internal interrupt that has highest priority among all the interrupts except the Divide By Zero (Type 0) exception.

22. In case of string instructions, the NMI interrupt will be served only after
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
Answer: c
Explanation: When NMI is activated, the current instruction being executed is completed and then NMI is served. In the case of string instructions, it is served after the complete string is manipulated.

23. The NMI pin should remain high for atleast
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
Answer: d
Explanation: The NMI pin should remain high for atleast 2 clock cycles and need not be synchronized with the clock for being sensed.

24. The INTR signal can be masked by resetting the
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
Answer: b
Explanation: The INTR signal can be masked by resetting the interrupt flag.

25. For the INTR signal, to be responded to in the next instruction cycle, it must go ________ in the last clock cycle of the current instruction
a) high
b) low
c) high or low
d) unchanged
Answer: a
Explanation: The INTR signal must go high in the clock cycle of the current instruction in order to respond in the next instruction cycle.

26. The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
Answer: d
Explanation: At the end of each instruction, the status of the pending interrupts is checked.

27. Once the processor responds to an INTR signal, the IF is automatically
a) set
b) reset
c) high
d) low
Answer: b
Explanation: The IF is automatically reset when the processor responds to an INTR signal. If the processor wants to respond to any type of INTR signal further then, the IF should again be set.

28. If the pin LOCK (active low based) is low at the trailing edge of the first ALE pulse, then till the start of the next machine cycle, the pin LOCK (active low) is
a) low
b) high
c) low or high
d) none of the mentioned
Answer: a
Explanation: The pin LOCK (active low) remains low till the start of the next machine cycle.

29. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
Answer: c
Explanation: The INTA (active low) goes low and remains low for two clock cycles before returning back to the high state.

30. If a number of instructions are repeating through the main program, then to reduce the length of the program, __________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned
Answer: c
Explanation: For a certain number of instructions that are repeated in the main program, when macro is defined then the code of a program is reduced by placing the name of the macro at which the set of instructions are needed to be repeated.

31. The process of assigning a label or macroname to the string is called
a) initialising macro
b) initialising string macro
c) defining a string macro
d) defining a macro
Answer: d
Explanation: The process of assigning a label to the string is called defining a macro.

32. A macro within a macro is called
a) macro-within-macro
b) nested macro
c) macro-in-macro
d) none of the mentioned
Answer: b
Explanation: A macro may be called from inside a macro. This type of macro is called nested macro.

33. A macro can be defined as
a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program
Answer: d
Explanation: A macro can be defined anywhere in a program.

34. A macro can be used as ________
a) in data segment
b) to represent directives
c) to represent statements
d) all of the mentioned
Answer: d
Explanation: A macro may be used in data segment and can also be used to represent statements and directives.

35. The end of a macro can be represented by the directive.
a) END
b) ENDS
c) ENDM
d) ENDD
Answer: c
Explanation: The ENDM directive marks the end of the instructions or statements sequence assigned with the macro name.
36. Inserting the statements and instructions represented by macro, directly at the place of the macroname, in the program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
d) none of the mentioned
Answer: a
Explanation: Inserting the statements and instructions at the place of macroname, in the program, is known as calling a macro.

37. The time required for execution of a macro is ________ that of the procedure.
a) greater than
b) less than
c) equal to
d) none of the mentioned
Answer: b
Explanation: The time required for execution of a macro is less than that of procedure as it does not contain CALL and RET instructions as the procedures do.

38. Which of the following statements is incorrect?
a) complete code of instruction string is inserted at each place, wherever the macroname appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics
Answer: c
Explanation: Macro does not require stack memory and hence has less time for execution.

39. The beginning of the macro can be represented as
a) START
b) BEGIN
c) MACRO
d) None of the mentioned
Answer: c
Explanation: The beginning of the macro is represented as macroname followed by the directive MACRO.
SYNTAX: macroname MACRO
EXAMPLE: STRINGS MACRO.

40. If ‘n’ denotes the number of clock cycles and ‘T’ denotes period of the clock at which the microprocessor is running, then the duration of execution of loop once can be denoted by
a) n+T
b) n-T
c) n*T
d) n/T
Answer: c
Explanation: The duration of execution of the loop is the product of number of clock cycles and the period of the clock cycle at which microprocessor is running.

41. The number of instructions actually executed by the microprocessor depends on the
a) stack
b) loop count
c) program counter
d) time duration
Answer: b
Explanation: As the microprocessor executes each instruction corresponding loop counter value decreases and the microprocessor executes the instructions till the loop counter becomes zero.

42. In case of subroutines, the actual number of instructions executed by the processor depends on
a) loop count
b) length of interrupt service routine
c) length of procedure
d) none
Answer: c
Explanation: In case of subroutines or interrupt service routines, the number of instructions executed by the processor depends on the length of procedure (or subroutine) or length of interrupt service routine along with the main calling program.

43. The step included in generating delays is
a) determining exact required delay
b) selecting instructions for delay loop
c) finding period of clock frequency
d) all of the mentioned
Answer: d
Explanation: The delays can be generated step wise.

44. The Count, N can be defined as
a) required delay/duration for execution
b) duration of execution/required delay
c) required delay/number of clock cycles
d) required delay/period of clock frequency
Answer: a
Explanation: The count N can be defined as the required time delay by the duration for execution of the loop once.
Count, N = required delay (Td)/duration for execution of the loop once (n*T).

45. In the instruction set,

      MOV CX, BA03H
WAIT: DEC CX
      NOP
      JNZ WAIT
      RET

if the zeroth condition is satisfied then, for execution, the JNZ instruction takes
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
Answer: d
Explanation: The JNZ instruction takes only 4 clock cycles if the zeroth condition is satisfied.

46. In the instruction set,

      MOV CX, BA03H
WAIT: DEC CX
      NOP
      JNZ WAIT
      RET

if the zeroth condition is not satisfied, then the JNZ instruction takes
a) 2 clock cycles
b) 8 clock cycles
c) 16 clock cycles
d) 64 clock cycles
Answer: c
Explanation: The JNZ instruction takes 16 clock cycles if the zeroth condition is not satisfied.

47. The maximum count value of 16-bit count register puts a limitation on
a) memory usage
b) storage of address of registers
c) to generate clock pulse
d) to generate maximum delay
Answer: d
Explanation: The maximum count value of 16-bit count register is FFFFH. This may put the limitation on the maximum delay that can be generated using the instructions.

48. When large delays are required, then to serve the purpose
a) one or more count registers can be used
b) one or more shift registers can be used
c) one or more pointer registers can be used
d) one or more index registers can be used
Answer: a
Explanation: One or more count registers can be used to serve large delays.

49. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.

50. The example of output device is
a) CRT display
b) 7-segment display
c) Printer
d) All of the mentioned
Answer: d
Explanation: The output device transfers data from the microprocessor to the external devices.

51. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar to write operation.

52. The operation, IOWR (active low) performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
Answer: b
Explanation: IOWR (active low) operation means writing data to an output device and not an input device.

53. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
c) good output port
d) bad output port
Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So, the latch is used as it acts as a good output port.

54. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to avoid loading.

55. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
Answer: d
Explanation: A tristate buffer is used as an input device to overcome loading.

56. The chip 74LS245 is
a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
Answer: d
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used as an 8-bit input port. But while using as an input device, only one direction is useful.

57. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
Answer: a
Explanation: If DIR is 1, then the direction is from A(inputs) to B(outputs).

58. In memory-mapped scheme, the devices are viewed as
a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are addressed likewise.

59. Programmable peripheral input-output port is another name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
Answer: b
Explanation: The parallel input-output port chip 8255 is also known as programmable peripheral input-output port.

60. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
Answer: c
Explanation: Port C can function independently either as input or as output ports.

61. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned
Answer: c
Explanation: By programming the bits of control word register, the operations of the ports are specified.

62. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
d) none of the mentioned
Answer: b
Explanation: The data bus buffer is controlled by read/write control logic.

63. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR(ACTIVE LOW)
d) All of the mentioned
Answer: d
Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs provided by the microprocessor to the read/write control logic of 8255.

64. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none of the mentioned
Answer: c
Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution of input or output instructions by the microprocessor.

65. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper
Answer: d
Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.

66.. If A1=0, A0=1 then the input read cycle is performed from
a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus
Answer: b
Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.

67. The function, ‘data bus tristated’ is performed when
a) CS(active low) = 1
b) CS(active low) = 0
c) CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
d) CS(active low) = 1 OR CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
Answer: d
Explanation: The data bus is tristated when chip select pin=1 or chip select pin=0 and read and write signals are high i.e 1.

68. The pin that clears the control word register of 8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK
Answer: c
Explanation: If reset pin is enabled then the control word register is cleared.

69. In the I/O mode, the 8255 ports work as
a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
View Answer
Answer: c
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.

70. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
Answer: c
Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port bits.

71. The feature of mode 0 is
a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
Answer: d
Explanation: In mode 0, any port can be used as input or output and output ports are latched.

72. The strobed input/output mode is another name of
a) mode 0
b) mode 1
c) mode 2
d) none
Answer: b
Explanation: In this mode, the handshaking signals control the input or output action of the specified port.

73. If the value of the pin STB (Strobe Input) falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
Answer: a
Explanation: If the value of the pin STB (Strobe Input) falls to low level, the input port is loaded into input latches.

74. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) Control word register
b) CPU
c) Printer
d) Ports
Answer: c
Explanation: This signal indicates that the printer is selected.

75. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
Answer: d
Explanation: The pulse width of the signal must be more than 50microseconds at the receiving terminal.

76. The level of the signal ERROR(active low) becomes ‘low’ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) All of the mentioned
Answer: d
Explanation: The level of the signal ERROR(active low) becomes ‘low’ when the printer is in the Paper end state, Offline state and Error state.

77. The signals that are provided to maintain proper data flow and synchronization between the data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
d) none
Answer: a
Explanation: Handshaking signals maintain proper data flow and synchronization.

78. The feature of mode 2 of 8255 is
a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned
Answer: d
Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.

79. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or delay generators.

80. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.

81. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.

82. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is reloaded and again the output becomes high and remains so for (N-1) clock pulses.

83. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the output remains high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse decrements it by 1 resulting in an even count value.

84. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Answer: b
Explanation: SC denotes select counter.

85. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.

86. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.

87. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.

80. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)

89.. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these five, four pins were alloted fixed vector addresses but the pin INTR was not alloted by vector address, rather an external device was supposed to hand over the type of the interrupt to the microprocessor.

90. The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request Register internally.

91. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request Register) at the direction of the Priority Resolver.

92. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all the operations that are involved within the interrupts like accepting and managing interrupt acknowledge signals, interrupts.

93. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64 vectored interrupts can be provided.

94. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a buffer enable to control buffer transreceivers. If it is not used in buffered mode, then the pin is used as input to designate whether the chip is used as a master or a slave.

95. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Answer: d
Explanation: The initialization procedure involves
i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.

96. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will automatically reset the highest ISR.

97. In the application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the applications where all the interrupting devices are of equal priority.
iii) choosing binary or BCD counters
iv) loading of the counter registers.

1. The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the active edge of EOC(end of conversion) signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent digital data output from the moment of the start of conversion is called conversion delay.

2. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
Answer: c
Explanation: Successive approximation and dual slope integration are the most popular techniques that are used in the integrated ADC chips.

3. The procedure of algorithm for interfacing ADC contain
a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring the stability of analog input, issuing start of conversion pulse to ADC, reading end of conversion signal to mark the end of a conversion process, reading digital data output of ADC as equivalent digital output.

4. Which is the ADC among the following?
a) AD 7523
b) 74373
c) 74245
d) ICL7109
Answer: d
Explanation: AD 7523 is a DAC(Digital to analog converter), 74373 is a latch, 74245 is transceiver and ICL7109 is an ADC.

5. The conversion delay in a successive approximation of an ADC 0808/0809 is
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to other converters.

6. The number of inputs that can be connected at a time to an ADC that is integrated with successive approximation is
a) 4
b) 2
c) 8
d) 16
Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different analog inputs can be connected to the chip.

7. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow practical applications.

8. Which of the following is not one of the phases of the total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) disintegrate phase
Answer: b
Explanation: Autozero phase, signal integrate phase and disintegrate phase are the three phases of total conversion cycle.

9. Which of the following phase contain feedback loop in it?
a) autozero phase
b) signal integrate phase
c) disintegrate phase
d) none
Answer: a
Explanation: A feedback loop is closed around the system to charge the autozero capacitor to compensate for the offset voltages in the buffer amplifier, integrator and comparator.

10. In the signal integrate phase, the differential input voltage between IN LO(input low) and IN HI(input high) pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
Answer: c
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference between input low and input high.

11. Programmable peripheral input-output port is other name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
Answer: b
Explanation: The parallel input-output port chip 8255 is also known as programmable peripheral
input-output port.

12. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports
Answer: c
Explanation: Port C can function independently either as input or as output ports.

13. All the functions of the ports of 8255 are achieved by programming the bits of an internal
register called
a) data bus control
b) read logic control
c) control word register
d) none
Answer: c
Explanation: By programming the bits of control word register, the operations of the ports are
specified.

14. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
d) none
Answer: b
Explanation: The data bus buffer is controlled by read/write control logic.

15. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR(ACTIVE LOW)
d) all of the mentioned
Answer: d
Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs
provided by the microprocessor to the read/write control logic of 8255.

16. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none
Answer: c
Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the execution
of input or output instructions by the microprocessor.

17. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper
Answer: d
Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.

18. If A1=0, A0=1 then the input read cycle is performed from
a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus
Answer: b
Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.

19. The function, „data bus tristated‟ is performed when
a) CS(active low) =1
b) CS(active low) =0
c) CS(active low) =0, RD(active low) =1, WR(active low) =1
d) CS(active low) =1 OR CS(active low) =0, RD(active low) =1, WR(active low) =1
Answer: d
Explanation: the data bus is tristated when chip select pin=1 or chip select pin=0 and read and
write signals are high i.e 1.

20. The pin that clears the control word register of 8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK
Answer: c
Explanation: If reset pin is enabled then the control word register is cleared.

21. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.

22. The example of output device is
a) CRT display
b) 7-segment display
c) printer
d) all of the mentioned
Answer: d
Explanation: The output device transfers data from microprocessor to the external devices.

23. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar to
write operation.

24. The operation, IOWR (active low) performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
Answer: b
Explanation: IOWR (active low) operation means writing data to an output device and not an
input device.

25. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
c) good output port
d) bad output port
Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So, the
latch is used as it acts as good output port.

26. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to
avoid loading.

27. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
Answer: d
Explanation: A tristate buffer is used as an input device to overcome loading.

28. The chip 74LS245 is
a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
Answer: d
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used
as an 8-bit input port. But while using as an input device, only one direction is useful.

29. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
Answer: a
Explanation: If DIR is 1, then the direction is from A(inputs) to B(outputs).

30. In memory-mapped scheme, the devices are viewed as
a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are
addressed likewise.

31. In the I/O mode, the 8255 ports work as
a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
Answer: c
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.

32. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
Answer: c
Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port
bits.

33. The feature of mode 0 is
a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
Answer: d
Explanation: In mode 0, any port can be used as input or output and output ports are latched.

34. The strobed input/output mode is another name of
a) mode 0
b) mode 1
c) mode 2
d) none
Answer: b
Explanation: In this mode, the handshaking signals control the input or output action of the
specified port.

35. If the value of the pin STB (Strobe Input) falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
Answer: a
Explanation: If the value of the pin STB (Strobe Input) falls to low level, then input port is
loaded into input latches.

36. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) control word register
b) CPU
c) Printer
d) ports
Answer: c
Explanation: This signal indicates that the printer is selected.

37. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
Answer: d
Explanation: The pulse width of the signal must be more than 50microseconds at the receiving
terminal.

38. The level of the signal ERROR(active low) becomes „low‟ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) all of the mentioned
Answer: d
Explanation: The level of the signal ERROR(active low) becomes „low‟ when the printer is in
Paper end state, Offline state and Error state.

39. The signals that are provided to maintain proper data flow and synchronisation between the
data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
d) none
Answer: a
Explanation: Handshaking signals maintain proper data flow and synchronisation.

40. The feature of mode 2 of 8255 is
a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned
Answer: d
Explanation: In mode 2 of 8255, single 8-bit port is available i.e group A.
ADC

41. The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the
active edge of EOC(end of conversion) signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent digital
data output from the moment of the start of conversion is called conversion delay.

42. The popular technique that is used in the integration of ADC chips is
a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
Answer: c
Explanation: Successive approximation and dual slope integration are the most popular
techniques that are used in the integrated ADC chips.

43. The procedure of algorithm for interfacing ADC contain
a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring stability of analog
input, issuing start of conversion pulse to ADC, reading end of conversion signal to mark the end
of conversion process, reading digital data output of ADC as equivalent digital output.

44. Which is the ADC among the following?
a) AD 7523
b) 74373
c) 74245
d) ICL7109
Answer: d
Explanation: AD 7523 is a DAC(Digital to analog converter), 74373 is a latch, 74245 is
transreceiver and ICL7109 is an ADC.

45. The conversion delay in successive approximation of an ADC 0808/0809 is
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to other
converters.

46. The number of inputs that can be connected at a time to an ADC that is integrated with
successive approximation is
a) 4
b) 2
c) 8
d) 16
Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different
analog inputs can be connected to the chip.

47. ADC 7109 integrated by Dual slope integration technique is used for
a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow practical
applications.

48. Which of the following is not one of the phase of total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) deintegrate phase
Answer: b
Explanation: autozero phase, signal integrate phase and deintegrate phase are the three phases of
total conversion cycle.

49. Which of the following phase contain feedback loop in it?
a) autozero phase
b) signal integrate phase
c) deintegrate phase
d) none
Answer: a
Explanation: A feedback loop is closed around the system to charge the autozero capacitor to
compensate for the offset voltages in the buffer amplifier, integrator and comparator.

50. In the signal integrate phase, the differential input voltage between IN LO(input low) and IN
HI(input high) pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
Answer: c
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference
between input low and input high.

51. DAC (Digital to Analog Converter) finds application in
a) digitally controlled gains
b) motor speed controls
c) programmable gain amplifiers
d) all of the mentioned
Answer: d
Explanation: DAC is used in digitally controlled gains, motor speed controls and programmable
gain amplifiers.

52. To save the DAC from negative transients the device connected between OUT1 and OUT2 of
AD 7523 is
a) p-n junction diode
b) Zener
c) FET
d) BJT (Bipolar Junction transistor)
Answer: b
Explanation: Zener is connected between OUT1 and OUT2 pins of AD7523 to save from
negative transients.

53. An operational amplifier connected to the output of AD 7523 is used
a) to convert current output to output voltage
b) to provide additional driving capability
c) as current-to-voltage converter
d) all of the mentioned
Answer: d
Explanation: An operational amplifier is used as a current-to-voltage converter to convert current
output to output voltage and also provides additional driving capability to the DAC.

54. The DAC 0800 has a settling time of
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 microseconds
Answer: a
Explanation: DAC 0800 has a settling time of 100 milliseconds.

55. The device that is used to obtain an accurate position control of rotating shafts in terms of
steps is
a) DC motor
b) AC motor
c) Stepper motor
d) Servo motor
Answer: c
Explanation: Stepper motor employs rotation of its shaft in terms of steps, rather than continuous
rotation as in case of AC or DC motors.

56. The internal schematic of a typical stepper motor has
a) 1 winding
b) 2 windings
c) 3 windings
d) 4 windings
Answer: d
Explanation: the internal schematic of a typical stepper motor has 4 windings.

57. The number of pulses required for one complete rotation of the shaft of the stepper motor is
equal to the
a) number of internal teeth on a rotor
b) number of internal teeth on a stator
c) number of internal teeth on a rotor and stator
d) number of external teeth on a stator
Answer: a
Explanation: The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to the number of internal teeth on its rotor.

58. A simple scheme for rotating the shaft of a stepper motor is called
a) rotating scheme
b) shaft scheme
c) wave scheme
d) none
Answer: c
Explanation: In this scheme, the windings are applied with the required voltage pulses, in a
cyclic fashion.

59. The firing angles of thyristors are controlled by
a) pulse generating circuits
b) relaxation oscillators
c) microprocessor
d) all of the mentioned
Answer: d
Explanation: In early days, the firing angles were controlled by pulse generating circuits like
relaxation oscillators and now, they are accurately fired using a microprocessor.

60. The Isolation transformers are generally used for
a) protecting low power circuit
b) isolation
c) protecting low power circuit and isolation
d) none
Answer: c
Explanation: Any switching component of a high power circuit may be sufficient to damage the
microprocessor system. So, to protect the low power circuit isolation transformers are used. They
are also used if isolation is necessary.

61. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or delay generators.

62. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.

63. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as interrupt on terminal count.

64. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low
for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is
reloaded and again the output becomes high and remains so for (N-1) clock pulses.

65. The generation of square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the output remains
high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse
decrements it by 1 resulting in an even count value.

66. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Answer: b
Explanation: SC denotes select counter.

67. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: c
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.

68. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.

69. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.

70. The control word register contents are used for
a) initialising the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initialising the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.

71. The registers that store the keyboard and display modes and operations programmed by CPU
are
a) I/O control and data buffers
b) control and timing registers
c) return buffers
d) display address registers
Answer: b
Explanation: The control and timing registers store the keyboard and display modes and other
operations programmed by CPU.

72. The sensor RAM acts as 8-byte first-in-first-out RAM in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
Answer: c
Explanation: In this mode, each key code of the pressed key is entered in the order of the entry,
and in the meantime, read by the CPU, till the RAM becomes empty.

73. The registers that holds the address of the word currently being written by the CPU from the
display RAM are
a) control and timing register
b) control and timing register and timing control
c) display RAM
d) display address registers
Answer: d
Explanation: The display address registers holds the address of the word currently being written
or read by the CPU to or from the display RAM.

74. When a key is pressed, a debounce logic comes into operation in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: c
Explanation: In scanned keyboard mode with 2 key lockout mode of operation, when a key is
pressed, a debounce logic comes into operation. During the next two scans, other keys are
checked for closure and if no other key is pressed then the first pressed key is identified.

75. The mode that is programmed using “end interrupt/error mode set command” is
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: a
Explanation: The scanned keyboard special error mode is programmed using end interrupt/error
mode set command. This mode is valid only under the N-key rollover mode.

76. When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks
whether the key is still depressed in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Answer: b
Explanation: In this mode, When a key is pressed, the debounce circuit waits for 2 keyboard
scans and then checks whether the key is still depressed. If it is still depressed, the code is
entered in FIFO RAM.

77. The data that is entered from the left side of the display unit is of
a) left entry mode
b) right entry mode
c) left and right entry modes
d) none
Answer: a
Explanation: The data that is entered from the left side of the display unit is of left entry mode, as
in a type-writer the first character typed appears at the left-most position, while the subsequent
characters appear successively to the right of the first one.

78. The FIFO status word is used to indicate the error in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
Answer: c
Explanation: Overrun error occurs, when an already full FIFO is attempted an entry. Underrun
error occurs when an empty FIFO read is attempted.

79. The flag that increments automatically after each read or write operation to the display RAM is
a) IF
b) RF
c) AI
d) WF
Answer: c
Explanation: AI refers to auto increment flag.

80. If any change in sensor value is detected at the end of a sensor matrix scan, then the IRQ line
a) goes low
b) goes high
c) remains unchanged
d) none
Answer: b
Explanation: In sensor matrix mode, the IRQ line goes high, if any change in sensor value is
detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read by
the CPU.

81. A/D converter is used for __________
a) converting analog to digital
b) converting digital to analog
c) converting digital to mixed signal mode
d) converting analog to mixed signal mode
Answer: a
Explanation: In a digital data acquisition system, an A/D converter is used for the purpose of converting analog signals to digital.

82. Output of A/D converter is _________
a) given to an analog display
b) given to a digital display
c) given to a CRO
d) given to a voltmeter
Answer: b
Explanation: Output from the analog to digital converter is given to a digital display device or to a digital recorder for the purpose of displaying or recording.

83. What are auxiliary equipments?
a) equipment
b) guard rings
c) devices
d) voltage source
Answer: c
Explanation: Auxiliary equipments are basically devices used for system programming functions and digital data processing applications.

84. What is the main function of auxiliary equipment?
a) unit step response
b) ramp response
c) non-linear response
d) linear response
Answer: d
Explanation: The typical functions of auxiliary equipments include linearization and limit compression for the input signals. Individual instruments or a digital computer is used to perform these functions.

85. What is a digital recorder?
a) records digital data
b) records analog data
c) does not record data
d) records both analog and digital data
Answer: a
Explanation: A digital recorder is used for the purpose of recording the digital data. Punched cards, magnetic tape recorders, type written pages, etc make use of digital recorders.

86. Data acquisition systems are not widely used.
a) True
b) False
Answer: b
Explanation: In digital recorders, data acquisition systems are used widely in industries, space applications, medical and telephony.

87. For lower accuracies _________
a) digital acquisition system is used
b) both digital and analog acquisition systems are used
c) analog acquisition system is used
d) mechanical data acquisition system is used
Answer: c
Explanation: When low values of accuracy is required, analog data acquisition system is used. This includes a wide frequency bandwidth as well.

88. Digital acquisition systems are used when _________
a) bandwidth is high
b) bandwidth is medium
c) bandwidth is zero
d) bandwidth is low
Answer: d
Explanation: When the bandwidth required is low, usually digital acquisition systems are made use of. For higher accuracy and lower per channel cost, digital data acquisition systems are used.

1. The unit that executes all the numeric processor instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
Answer: c
Explanation: The 8087 is divided into two sections namely control unit and numeric extension unit in which the numeric extension unit executes all the numeric processor instructions.

2. The unit that receives and decodes the instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned
Answer: a
Explanation: The control unit receives, decodes the instructions, and executes the 8087 control instructions.

3. The control unit functions in
a) establishing communication between CPU and memory
b) coordinating the internal coprocessor execution
c) reads and writes memory operands
d) all of the mentioned
Answer: d
Explanation: The control unit is used for establishing communication between CPU and memory and coordinating the internal coprocessor execution.

4. When the numeric extension unit (NEU) begins its execution, then the signal that is active is
a) BUSY (active high)
b) BUSY (active low)
c) READY (active low)
d) RESET (active high)
Answer: a
Explanation: When NEU begins its execution, the BUSY signal is pulled up. Also, this output signal when high, indicates to the CPU that it is busy with the execution of an allotted instruction.

5. The register that allows the register programmer to select the required processing options is
a) significant
b) exponent
c) control word register
d) none of the mentioned
Answer: c
Explanation: The control word register allows the register programmer to select the required processing options out of available ones. It is used to control the operation of 8087.

6. Invalid operation is the exception generated due to
a) stack overflow
b) stack underflow
c) indeterminate form as result
d) all of the mentioned
Answer: d
Explanation: Invalid operation is generated due to stack overflow, stack underflow, indeterminate form as result, or non-number (NAN) as operand.

7. The exception generated for a too big result to fit in the format is
a) invalid operation
b) overflow
c) denormalized operand
d) result overflow
Answer: b
Explanation: A too big result to fit in the format generates this exception. The condition code bits indicate that the result is prohibitively large.

8. If the result is infinity, then the exception generated is
a) overflow
b) invalid operation
c) denormalized operand
d) zero divide
Answer: d
Explanation: If any non-zero finite operand is divided by zero, the zero divide exception is generated. The resulting condition code bits indicate that the result is infinity, even if the exception is masked.

9. To operate 8087 in maximum mode, the pin MN/MX (active low) is
a) connected to Vcc or power supply
b) connected to ground
c) left unconnected
d) none of the mentioned
Answer: b
Explanation: The 8087 can operate in a maximum mode, only when the MN/MX (active low) pin of the CPU is grounded. In maximum mode, all the control signals are derived using a sequence chip known as a bus controller.

10. If the result is rounded according to the rounding control bits, then the exception generated is
a) denormalized operand
b) underflow
c) inexact result
d) invalid operation
Answer: c
Explanation: If it is impossible to fit the actual result in the specified format, the result is rounded according to the rounding control bits, and an exception is generated. This sets the precision exception flag.

11. The instruction that stores a copy of top of the stack into the memory, and pops the top of the stack is
a) FST
b) FSTP
c) FIST
d) FLD
Answer: b
Explanation: FSTP (store floating point number and pop) stores a copy of top of the stack into memory or any coprocessor register, and then pops the top of the stack.

12. The instruction that multiplies the content of the stack top by 2n is
a) FMUL
b) FPREM
c) FSCAL
d) FCSH
Answer: c
Explanation: FSCAL instruction multiplies the content of the stack top by 2n, where n is an integral part of stack and stores the result in stack.

13. If the opcode bit is D=1, then the source and destination operands are
a) incremented
b) decremented
c) cleared
d) interchanged
Answer: d
Explanation: If D=1, then it interchanges the source and destination operands.

14. Which of the following is not a block of an architecture of 80287?
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
Answer: d
Explanation: The three blocks of an internal architecture of 80287 are:
1. bus control logic
2. data interface and control unit
3. floating point unit.

15. The unit that provides and controls the interface, between the internal 80287 bus and 80286 bus via data buffer is
a) bus control logic
b) data interface and control unit
c) floating point unit
d) none of the mentioned
Answer: a
Explanation: The bus control logic provides and controls the interface, between the internal 80287 bus and 80286 bus via data buffer.

16. The data interface and control unit consists of
a) status and control words
b) tag words and error pointers
c) instruction decoders
d) all of the mentioned
Answer: d
Explanation: The data interface and control unit contains status and controls words, TAG words and error pointers.

17. The word that optimizes the NDP performance, by maintaining a record of empty and non-empty register locations is
a) Status and control words
b) TAG words
c) Error pointers
d) All of the mentioned
Answer: b
Explanation: The TAG word optimizes the NDP performance by maintaining a record of empty and non-empty register locations. It helps the exception handler to identify special values in the contents of the stack locations.

18. The part of the data interface and control unit, that points to the source of exception generated is
a) Status and control words
b) TAG words
c) Error pointers
d) None of the mentioned
Answer: c
Explanation: The error pointers point to the source of exception (address of the instruction that generated the exception) generated.

19. The data bus in a floating point unit is of
a) 16 bits
b) 32 bits
c) 64 bits
d) 84 bits
Answer: d
Explanation: The data bus in a floating point unit is of 84-bits. Out of this 84-bits, the lower 68 bits are significant (mantissa) data bit, the next 16 bits are used for the exponent.

20. The arrangement of data that is to be shifted successively, whenever required for the execution, is done by
a) error pointer
b) data buffer
c) barrel shifter
d) none of the mentioned
Answer: c
Explanation: The barrel shifter arranges and presents the data to be shifted successively, whenever required for the execution.

21. The word that is used to select one of the processing options, among the provided ones is
a) status word
b) control word
c) status and control words
d) none of the mentioned
Answer: b
Explanation: The control word is used to select one of the processing options, among the ones provided by 80287.

22. After reset of 80287, the control bit that is initialized to zero is
a) masking bits
b) precision control bits
c) rounding control bits
d) infinity control bits
Answer: d
Explanation: The infinity control bit is initialized to zero after reset.

23. The bits that are modified depending upon the result of the execution of arithmetic instructions are
a) masking bits
b) rounding control bits
c) condition code bits
d) error summary bits
Answer: c
Explanation: The condition code bits are similar to the flags of a CPU. These are modified depending upon the result of the execution of arithmetic instructions.

24. If the stack flag is set, and condition code bit C1=1, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: b
Explanation: If the stack flag is set, and condition code bit C1=1, then the stack has overflown.

25. If the stack flag is set, and condition code bit C1=0, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: c
Explanation: If the stack flag is set, and condition code bit C1=0, then the stack has underflown.

26. The bits that affect the result of arithmetic operations like ADD, SUB, MUL, DIV are
a) condition code bits
b) rounding control bits
c) masking bits
d) precision control bits
Answer: d
Explanation: The precision control bits affect ADD, SUB, MUL, DIV and SQRT results.

27. The precision is decided by the
a) opcode
b) extended precision format
c) opcode or extended precision format
d) none of the mentioned
Answer: c
Explanation: For other than the arithmetic instructions (like ADD, SUB, MUL, DIV and SQRT), the precision is decided by opcode or extended precision format.

28. If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: c
Explanation: If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from 80286 to 80287.

29. If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: b
Explanation: If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from 80287 to 80286.

30. Which of the input line(s) indicate that the CPU is performing an escape operation, and enables 80287 to execute the next instruction?
a) NPWR (active low) and NPRD (active low)
b) NPS1 and NPS2 (active low)
c) NPS1 (active low) and NPS2
d) CMD0 and CMD1
Answer: c
Explanation: The Numeric Processor select input lines, NPS1 (active low) and NPS2, indicate that the CPU is performing an escape operation, and enables 80287 to execute the next instruction.

31. For which pin of 80286 is the active low pin, BUSY of 80287, connected?
a) ERROR (active low)
b) BUSY (active low)
c) HLDA
d) TEST (active low)
Answer: d
Explanation: The BUSY (active low) is connected to the TEST (active low) pin of 80286.

32. If Clock Mode (CM) input pin is held low, then the CLK input is divided by
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: If Clock Mode (CM) input pin is held high, then the CLK input is directly used for deriving the internal timings. Else, it is divided by 2.

33. Which of the following pin is not involved in the interface of 80287 with 80286?
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: c
Explanation: The 10 pins, PEREQ, PEACK#, BUSY#, ERROR#, NPRD(active low)#, NPWR(active low)#, NPS1(active low)#, NPS2#, CMD0 and CMD1.

34. The PEACK (active low) when activated, the pin that goes into deactivation is
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: a
Explanation: When the data transfer is over, the CPU activates PEACK (active low)# pin, which results in deactivating the PEREQ pin by 80287.

35. If the stack flag is set, and condition code bit C1=1, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: b
Explanation: If the stack flag is set, and condition code bit C1=1, then the stack has overflown.

36. If the stack flag is set, and condition code bit C1=0, then the stack is
a) full
b) overflown
c) underflown
d) empty
Answer: c
Explanation: If the stack flag is set, and condition code bit C1=0, then the stack has underflown.

37. The bits that affect the result of arithmetic operations like ADD, SUB, MUL, DIV are
a) condition code bits
b) rounding control bits
c) masking bits
d) precision control bits
Answer: d
Explanation: The precision control bits affect ADD, SUB, MUL, DIV and SQRT results.

38. The precision is decided by the
a) opcode
b) extended precision format
c) opcode or extended precision format
d) none of the mentioned
Answer: c
Explanation: For other than the arithmetic instructions (like ADD, SUB, MUL, DIV and SQRT), the precision is decided by opcode or extended precision format.

39. If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: c
Explanation: If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from 80286 to 80287.

40. If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287
Answer: b
Explanation: If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from 80287 to 80286.

41. Which of the input line(s) indicate that the CPU is performing an escape operation, and enables 80287 to execute the next instruction?
a) NPWR (active low) and NPRD (active low)
b) NPS1 and NPS2 (active low)
c) NPS1 (active low) and NPS2
d) CMD0 and CMD1
Answer: c
Explanation: The Numeric Processor select input lines, NPS1 (active low) and NPS2, indicate that the CPU is performing an escape operation, and enables 80287 to execute the next instruction.

42. For which pin of 80286 is the active low pin, BUSY of 80287, connected?
a) ERROR (active low)
b) BUSY (active low)
c) HLDA
d) TEST (active low)
Answer: d
Explanation: The BUSY (active low) is connected to the TEST (active low) pin of 80286.

43. If Clock Mode (CM) input pin is held low, then the CLK input is divided by
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: If Clock Mode (CM) input pin is held high, then the CLK input is directly used for deriving the internal timings. Else, it is divided by 2.

44. Which of the following pin is not involved in the interface of 80287 with 80286?
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: c
Explanation: The 10 pins, PEREQ, PEACK#, BUSY#, ERROR#, NPRD(active low)#, NPWR(active low)#, NPS1(active low)#, NPS2#, CMD0 and CMD1.

45. The PEACK (active low) when activated, the pin that goes into deactivation is
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1
Answer: a
Explanation: When the data transfer is over, the CPU activates PEACK (active low)# pin, which results in deactivating the PEREQ pin by 80287.

46. The semiconductor memories are organised as __________ dimension(s) of array of memory locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none
Answer: b
Explanation: The semiconductor memories are organised as two dimensions of an array which consists of rows and columns.

47. If a location is selected, then all the bits in it are accessible using a group of conductors called
a) control bus
b) address bus
c) data bus
d) either address bus or data bus
Answer: c
Explanation: The bits in a selected location are accessible using data bus.

48. To address a memory location out of N memory locations, the number of address lines required is
a) log N (to the base 2)
b) log N (to the base 10)
c) log N (to the base e)
d) log (2N) (to the base e)
Answer: a
Explanation: For n memory locations, log n(to the base of 2) address lines are required. For addressing 4K bytes of memory, 12 address lines are required since log(4KB) =log(4*1024)=log(2¹²)=12.

49. If the microprocessor has 10 address lines, then the number of memory locations it is able to address is
a) 512
b) 1024
c) 2048
d) none
Answer: b
Explanation: Since for n address lines, the number of memory locations able to address is 2^n.

50. In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
a) upper address memory bank
b) even address memory bank
c) static upper memory
d) odd address memory bank
Answer: d
Explanation: In static memory, the upper 8-bit bank is called odd address memory bank.

51. In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
a) lower address memory bank
b) even address memory bank
c) static lower memory bank
d) odd address memory bank
Answer: b
Explanation: In static memory, the lower 8-bit bank is called even address memory bank.

52. In most of the cases, the method used for decoding that may be used to minimise the required hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none
Answer: c
Explanation: In general, linear decoding is used to minimise the required hardware.

53. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
Answer: a
Explanation: The two 4K*8 chips of RAM and ROM are arranged in parallel.

54. If (address line) Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM
Answer: c
Explanation: If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in RAM.

55. If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
a) RAM
b) ROM
c) RAM and ROM
d) ONLY RAM
Answer: c
Explanation: If at a time Ao and BHE(active low) both are zero, then both RAM and ROM are selected.