## [MCQ] Linear Integrated Circuit

Exit Intent

#### Module 1

1. Determine the output from the following circuit

a) 180o in phase with input signal
b) 180o out of phase with input signal
c) Same as that of input signal
d) Output signal cannot be determined
Explanation: The input signal is given to the inverting input terminal. Therefore, the output Vo is 180o out of phase with input signal V2.

2. Which of the following electrical characteristics is not exhibited by an ideal op-amp?
a) Infinite voltage gain
b) Infinite bandwidth
c) Infinite output resistance
d) Infinite slew rate
Explanation: An ideal op-amp exhibits zero output resistance so that output can drive an infinite number of other devices.

3. An ideal op-amp requires infinite bandwidth because
a) Signals can be amplified without attenuation
b) Output common-mode noise voltage is zero
c) Output voltage occurs simultaneously with input voltage changes
d) Output can drive infinite number of device
Explanation: An ideal op-amp has infinite bandwidth. Therefore, any frequency signal from 0 to ∞ Hz can be amplified without attenuation.

4. Ideal op-amp has infinite voltage gain because
a) To control the output voltage
b) To obtain finite output voltage
c) To receive zero noise output voltage
d) None of the mentioned
Explanation: As the voltage gain is infinite, the voltage between the inverting and non-inverting terminal (i.e. differential input voltage) is essentially zero for finite output voltage.

5. Determine the output voltage from the following circuit diagram?

a)
b)
c)
d) None of the mentioned
Explanation: In an ideal op-amp when the inverting terminal is zero. The output will be in-phase with the input signal.

6. Find the output voltage of an ideal op-amp. If V1 and V2 are the two input voltages
a) VO= V1-V2
b) VO= A×(V1-V2)
c) VO= A×(V1+V2)
d) VO= V1×V2
Explanation: The output voltage of an ideal op-amp is the product of gain and algebraic difference between the two input voltages.

7. How will be the output voltage obtained for an ideal op-amp?
a) Amplifies the difference between the two input voltages
b) Amplifies individual voltages input voltages
c) Amplifies products of two input voltage
d) None of the mentioned
Explanation: Op-amp amplifies the difference between two input voltages and the polarity of the output voltage depends on the polarity of the difference voltage.

8. The signal to an inverting terminal of an ideal op-amp is zero. Find the output voltage, if the other input voltage is

a)
b)
c)
d) Data provided is insufficient
Explanation: Although the output is 180o out of phase with input signal, the gain of the amplifier is not given.

9. Which is not the ideal characteristic of an op-amp?
a) Input Resistance –> 0
b) Output impedance –> 0
c) Bandwidth –> ∞
d) Open loop voltage gain –> ∞
Explanation: Input resistance is infinite so almost any signal source can drive it and there is no loading of the preceding stage.

10. Find the input voltage of an ideal op-amp. It’s one of the inputs and output voltages are 2v and 12v. (Gain=3)
a) 8v
b) 4v
c) -4v
d) -2v
Explanation: The output voltage, VO = (Vin1– Vin2)
=> 12v=3×(2- Vin2)
=> Vin2= -2v.

11. Which factor determine the output voltage of an op-amp?
a) Positive saturation
b) Negative saturation
c) Both positive and negative saturation voltage
d) Supply voltage
Explanation: Output voltage is proportional to input voltage only until it reaches the saturation voltage. The output cannot exceed the positive and negative saturation voltage. These saturation voltages are specified by an output voltage swing rating of the op-amp for given values of supply voltage.

12. A feedback amplifier is also called as
a) Open loop amplifier
b) Closed loop amplifier
c) Feedback network amplifier
d) Looped network amplifier
Explanation: A feedback amplifier is sometimes referred as a closed loop amplifier because the feedback forms a closed loop between input and the output.

13. How many types of configuration are available for feedback amplifier?
a) Six
b) Four
c) Two
d) Eight
Explanation: There are four type of configuration are available. They are voltage series feedback, voltage shunt feedback, Current series feedback and Current shunt feedback.

14. Which of the following is not a feedback configuration?
a) Current-series feedback
b) Voltage-shunt feedback
c) Current-Voltage feedback
c) Current-Shunt feedback
Explanation: In a feedback amplifier, either current or voltage can be fed back to the input, but both current and voltage cannot be feedback simultaneously.

15. When load current flows into the feedback circuit, the configuration is said to be
a) Current-shunt feedback
b) Voltage-shunt feedback
c) Voltage-series feedback
d) All of the mentioned
Explanation: In current-series and current-shunt feedback circuit, the load current flows into the feedback circuit.

16. Find the voltage-series feedback amplifier from the given diagram?

Explanation: The mentioned diagram is the voltage-series feedback amplifier because the voltage across load resistor is the input voltage to the feedback circuit.

17. On what criteria does the feedback amplifier are classified?
a) Signal fed back to input
b) Signal applied to input
c) Signal fed back to output
d) None of the mentioned
Explanation: The feedback amplifiers are classified according to whether the voltage or current is fed back to the input in series or in parallel.

18. The closed-loop voltage gain is reciprocal of
a) Voltage gain of op-amp
b) Gain of the feedback circuit
c) Open loop voltage gain
d) None of the mentioned
Explanation: Comparing the equation of closed loop voltage gain (AF) and the gain of the feedback circuit (B). AF is reciprocal of B
=> AF = 1+( RF/ R1) ; B= R1/( R1+ RF)
=> B = 1+( R1/ RF)
Therefore, AF = 1/B.

19. Select the specifications that implies the inverting amplifier?
a) V1 = -3v, V2 = -4v
b) V1 = -2v, V2 = 3v
c) V1 = 5v, V 2 = 15v
d) V1 = 0v, V2 = 5v
Explanation: In inverting amplifier, the input is applied to the inverting terminal and the non-inverting terminal is grounded. So,the input applied to inverting amplifier can be V1 = 0v, V2 = 5v.

20. Open-loop op-amp configuration has
a) Direct network between output and input terminals
b) No connection between output and feedback network
c) No connection between input and feedback network
d) All of the mentioned
Explanation: In an open loop configuration, the output signal is not fed back in any form as part of the input signal and the loop that would have been formed with feedback is open.

21. In which configuration does the op-amp function as a high gain amplifier?
a) Differential amplifier
b) Inverting amplifier
c) Non-inverting amplifier
d) All of the mentioned
Explanation: An op-amp functions as a high gain amplifier when connected in open loop configuration. These three are the open loop configuration of an op-amp.

22. How does the open loop op-amp configuration classified?
a) Based on the output obtained
b) Based on the input applied
c) Based on the amplification
d) Based on the feedback network
Explanation: Open loop configurations are classified according to the number of inputs used and the terminal to which the input is applied when a single input is used.

23. What will be the voltage drop across the source resistance of differential amplifier when connected in open loop configuration?
a) Zero
b) Infinity
c) One
d) Greater than one
Explanation: The source resistances are normally negligible compared to the input resistance. Therefore, the voltage drop across input resistors can be assumed to be zero.

24. The output voltage of an open-loop differential amplifier is equal to
a) Double the difference between the two input voltages
b) Product of voltage gain and individual input voltages
c) Product of voltage gain and the difference between the two input voltages
d) Double the voltage gain and the difference between two input voltages
Explanation: The output voltage is equal to the voltage gain times the difference between the two input voltages.

25. Calculate the output voltage for the given circuit.

a) Vo = 7v
b) Vo = 5.9v
c) Vo = 12v
d) Vo = 11.4v
Explanation: The output voltage, Vo = A*(Vin1-Vin2).(Since, Rin1 and Rin2 are negligible compared to input resistance in open loop differential amplifier).
=> Vo = 4*(12v-9v) = 12v.

26. Find the output of inverting amplifier?
a) Vo = AVin
b) Vo = -AVin
c) Vo = -A(Vin1– Vin2)
d) None of the mentioned
Explanation: In an inverting amplifier the input signal is amplified by gain A and is also inverted at the output. The negative sign indicates that the output voltage is of opposite polarity.

27. Determine the output voltage for the non-inverting amplifier input voltage 37µVpp sinewave. Assume that the output is a 741.
a) -7.44 Vpp sinewave
b) 74 Vpp sinewave
c) 7.4Vpp sinewave
d) 0.7 Vpp sinewave
Explanation: The output voltage for non-inverting amplifier Vo = A*Vin = 200000 * 37µ = 7.4 Vpp sinewave.

28. Find the non-inverting amplifier configuration from the given circuit diagram?

Explanation: In a non-inverting amplifier, the input is applied to the non-inverting input terminal and the inverting terminal is connected to ground.

29. What happen if any positive input signal is applied to open-loop configuration?
a) Output reaches saturation level
b) Output voltage swing’s peak to peak
c) Output will be a sine waveform
d) Output will be a non-sinusoidal waveform
Explanation: In open-loop configuration, due to very high gain of the op-amp, any input signal slightly greater than zero drives the output to saturation level.

30. Why open-loop op-amp configurations are not used in linear applications?
a) Output reaches positive saturation
b) Output reaches negative saturation
c) Output switches between positive and negative saturation
d) Output reaches both positive and negative saturation
Explanation: When operated in open loop, the output switches between positive and negative saturation levels. For this reason, open loop op-amp configurations are not used in linear applications.

31. Why differential amplifiers are preferred for instrumentation and industrial applications?
a) Input resistance is low
b) Produce amplified output
c) Amplify individual input voltage
d) Reject common mode voltage
Explanation: Differential amplifiers are preferred in these applications because they are better able to reject common-mode voltage than single input circuits and present balanced input impedance.

32. Which of the following is a combination of inverting and non-inverting amplifier?
a) Differential amplifier with one op-amp
b) Differential amplifier with two op-amps
c) Differential amplifier with three op-amps
d) Differential amplifier with four op-amps
Explanation: In differential amplifier with one op-amp both the inputs are connected to separate voltage source. So, if any one of the source is reduced to zero, differential amplifier acts as an inverting or non-inverting amplifier.

33. What will be the output voltage when Vx =0v?
(Where Vx –> inverting input terminal of differential amplifier with one op-amp)
a) Vo = -(1+R F/R1)*V1
b) Vo = -(1- R F/ R1)*V1
c) Vo = (1+ R F/ R1)*V1
d) Vo = (R F/ R1)*V1
Explanation: When Vx =0v, the configuration is a non-inverting amplifier.

34. Compute the output voltage from the following circuit diagram?

a) -17v
b) -27v
c) -39v
d) -15v
Explanation: Since VB=0, the configuration becomes as an inverting amplifier. Hence, the output due to VA is
Vo = -(RF/R1)*VA = -(15kΩ/1.5kΩ)*2.7v = -10*2.7 = -27v.

35. Compute the output voltage if the input voltage is reduced to zero in differential amplifier with one op-amp?
a) Inverted Voltage
b) Same as the input voltage
c) Amplified inverted voltage
d) Cannot be determined
Explanation: It is not mentioned clearly whether inverting input or non-inverting input is reduced to zero. Therefore, the output cannot be determined.

36. The difference between the input and output voltage are -1v and 17v. Calculate the closed loop voltage gain of differential amplifier with one op-amp?
a) -51
b) 34
c) -17
d) 14
Explanation: Voltage gain of differential amplifier with one op-amp, AD=Output voltage / Difference of input voltage
=> AD = 17v/-1v = -17v.

37. For the differential amplifier given below, determine the Vx and RF value. Assume that the circuit is initially nulled.

a) Vx = -8v, RF = 9.9kΩ
b) Vx = 8v, RF = 9.9kΩ
c) Vx = -8v, RF = -9.9kΩ
d) Vx = 8v, RF = -9.9kΩ
Explanation: The closed loop voltage gain, AD = -(RF/R1)
=> RF = -3*3.3kΩ = -9.9kΩ
The net output is given is VO=-(RF /R1)*(Vx-Vy)
=> Vx= Vy– Vo (-R1 /RF)
=> Vx = 6+6(3.3kΩ/9.9kΩ) = 6+2 = 8v.

38. The gain of differential amplifier with one op-amp is same as that of
a) The inverting amplifier
b) The non-inverting amplifier
c) Both inverting and non-inverting amplifier
d) None of the mentioned
Explanation: The gain of differential amplifier is given as AD= -(RF /R1), which is equivalent to the output voltage obtained from the inverting amplifier.

39. Find the value of input resistance for differential amplifier with one op-amp. If R1 = R2=100Ω and RF = R3 =5kΩ.
a) RIFx = 110Ω; RIFy = 6.7kΩ
b) RIFx = 100Ω; RIFy = 5.1kΩ
c) RIFx = 150Ω; RIFy = 7.2kΩ
d) RIFx = 190Ω; RIFy = 9.0kΩ
Explanation: The input resistance of inverting amplifier is RIFx = (R1) and the input resistance of non-inverting amplifier is RIFy = (R2+ R3)
=> ∴ RIFx = 100Ω and
=> RIFy =100+5kΩ =5.1kΩ.

40. What is the net output voltage for differential amplifier with one op-amp
a) Vo = -(RF /R1)*Vx
b) Vo = -(RF /R1)*(Vx -Vy)
c) Vo = (1+RF /R1)*(Vx -Vy)
d) None of the mentioned
Explanation: The net output voltage for differential amplifier with one op-amp is given as Vo= -(RF /R1)*(Vx-Vy).

#### Module 2

1. Voltage to current converter is also called as
a) Current series positive feedback amplifier
b) Voltage series negative feedback amplifier
c) Current series negative feedback amplifier
d) Voltage series positive feedback amplifier
Explanation: Voltage to current converter is also called as current series negative feedback amplifier because the feedback voltage across internal resistor applied to the inverting terminal depends on the output current and is in series with the input difference voltage.

2. Given voltage to current converter with floating load. Determine the output current?

a) 3mA
b) 6mA
c) 4mA
d) 2mA
Explanation: Output current, Io = Vin /R1 = 10/5kΩ =2mA.

3. Which of the following application uses voltage to current converter?
a) Low voltage dc and ac voltmeter
b) Diode match finding
c) Light emitting diode
d) All of the mentioned
Explanation: In all the applications mentioned above, the input voltage Vin is converted into an output current of Vin/R1 or the input voltage appear across resistor.

4. The op-amp in low voltage DC voltmeter cannot be nullified due to
a) D’Arsonaval meter movement
b) Offset voltage compensating network
c) Selection of switch
d) Gain of amplifier
Explanation: The op-amp sometimes cannot be nullified because the output is very sensitive to even slight variation in wiper position of D’Arsonaval meter movement (ammeter with a full scale deflection of 1mA).

5. What is the maximum input voltage that has to be selected to calibrate a dc voltmeter with a full scale voltage range of 1-13v.
a) ≤ ±14v
b) ≥ ±13v
c) ≤ ±15v
d) = ±14v
Explanation: The maximum input voltage has to be ≤ ±14v, to obtain the maximum full scale input voltage of 13v.

6. Higher input voltage can be measured in low voltage DC voltmeter using
a) Smaller resistance value
b) Higher resistance value
c) Random resistance value
d) All of the mentioned
Explanation: Higher resistance values are required to measure relatively higher input voltage. For example, if the range of switch is at x10 position in the low voltage dc voltmeter then, the corresponding resistance value would be 10kΩ. So, it requires a 10v input to get a full scale deflection (if 1v cause full scale deflection in the ammeter with a full scale deflection of 1mA).

7. In the diagram given below, determine the deflection of the ammeter with a full scale deflection of 1mA when the switch is at X2kΩ. Consider resistance of the offset voltage compensating network to be 10Ω.

a) Full scale deflection in the ammeter
b) Half scale deflection in the ammeter
c) Quarter scale deflection in the ammeter
d) No deflection occurs in the ammeter
Explanation: Given Vin=1v ,R1=10+2kΩ ≅2kΩ
Io = Vin/R1= 1v/2kΩ =0.5mA. This means that 2v causes half scale deflection of the ammeter.

8. How to modify a low voltage DC voltmeter to low voltage ac voltmeter
a) Add a full wave rectifier in the feedback loop
b) Add a half wave rectifier in the feedback loop
b) Add a square wave rectifier in the feedback loop
b) Add a sine wave rectifier in the feedback loop
Explanation: A combination of an ammeter and a full wave rectifier can be employed in the feedback loop to form an ac voltmeter.

9. What makes the output voltage equals to zero in practical op-amp?
a) Input offset voltage
b) Output offset voltage
c) Offset minimizing voltage
d) Error voltage
Explanation: Input offset voltage is the differential input voltage that exists between two input terminals of an op-amp without any external input and force the output voltage to zero.

10. What happens due to mismatch between two input terminals in an op-amp?
a) Input offset voltage
b) Output offset voltage
c) Bothe the input and output offset voltage
d) None of the mentioned
Explanation: The input offset voltage in op-amp force the output voltage to zero due to the mismatch between two input terminal, there will be voltage produced at the output and this voltage is called output offset voltage.

11. Define polarity of the output offset voltage in a practical op-amp?
a) Positive polarity
b) Negative polarity
c) Positive or negative polarity
d) None of the mentioned
Explanation: The output offset voltage is a DC voltage, it may be positive or negative in polarity depending on whether the potential difference between two input terminal is positive or negative.

12. The input offset voltage of 741 op-amp has an absolute maximum value of 6mv, which means
a) Minimum difference between input terminals in 741 op-amp can be large as 6mv DC
b) Minimum difference between input terminals in 741 op-amp can be large as 6mv AC
c) Maximum difference between input terminals in 741 op-amp can be large as 6mv DC
d) Maximum difference between input terminals in 741 op-amp can be large as 6mv AC
Explanation: Given, the absolute maximum value for a 741 is Vio= 6mv. Therefore, voltage at the non-inverting input terminal may differ from that at the inverting input terminal by as much as 6mv dc. Also the output offset voltage is a DC voltage and it cannot be AC voltage.

13. If three different 741 op-amps are taken and the corresponding output offset voltage for each of them is measured. The output voltage in these three op-amps have
a) Same amplitude and polarity
b) Different amplitude and polarity
c) Same amplitude and different polarity
d) Different amplitude and same polarity
Explanation: Even though the op-amps are of the same type, the output voltage in these three op-amps are not of the same amplitude and polarity, because of mass production.

14. To reduce the output offset voltage VooT to zero
a) Input offset voltage compensating network is added at the inverting input terminal
b) Input offset voltage compensating network is added at the non-inverting input terminal
c) Input offset voltage compensating network is added at the output terminal
d) None of the mentioned
Explanation: To reduce the VooT to zero, the external circuit is added at the input terminal of the op-amp that will give the flexibility of obtaining input offset voltage of proper amplitude and polarity. The input terminal can be inverting or non-inverting.

15. Which of the following op-amp does not need compensating network?
a) 777
b) 741
c) 748
d) All of the mentioned
Explanation: The compensating network is not needed for these op-amps because, they have offset null pins.

16. Find out the voltage offset null circuit for the 741 op-amp?

Explanation: For 741-type op-amp, the manufacturer recommend a 10kΩ potentiometer be placed across offset null pin1 and 5 and a wiper be connected to the negative supply pin 4. Null output is obtained by adjusting the pot.

17. What will the condition of op-amp, before applying any external input
a) Compensated
b) Biased
c) Balanced
d) Zero
Explanation: Before applying external input to the op-amp, the output offset voltage should be reduced to zero with the help of an offset voltage compensating network. At this condition, the op-amp is said to be balanced or nulled.

18. Choose the compensating network design for non-inverting amplitude

Explanation: If an op-amp is used as an non-inverting amplifier, the compensating network should be connected to the inverting input terminal of the op-amp.

19. Find the thevenin’s equivalent for resistance and voltage?

a) 1-iii, 2-ii, 3-1
b) 1-ii, 2-I, 3-iii
c) 1-I, 2-ii, 3-iii
d) 1-ii, 2-iii, 3-i
Explanation: The maximum thevenin equivalent resistance Rmax occurs when the wiper is at the center of the potentiometer and the maximum thevenin equivalent voltage Vmax is equal to +Vcc or –Vee, when wiper is uppermost or lowest in the potentiometer.

20. What is done to compensate the voltage, when V1 > V2?

a) Move the wiper towards +Vcc
b) Move the wiper towards –Vee
c) Keep the wiper at the center of potentiometer
d) None of the mentioned
Explanation: V1 > V2 implies that output offset voltage is positive. This means that V2 should be increased until it is equal to V1. The wiper can be moved towards +Vcc until output offset voltage is reduced to zero.

21. Calculate the maximum thevenin equivalent resistance, if a 10kΩ potentiometer is used?
a) 0.4kΩ
b) 5 kΩ
c) 2.5kΩ
d) 4kΩ
Explanation: Rmax= Ra/2 || Ra/2 = Ra/4.
Given potentiometer, Ra = 10kΩ
=> Therefore, Rmax = 10kΩ/4 =2.5kΩ.

22. Find the input offset voltage for the circuit shown

a) Vio = (Rb*Vmax)/( Rmax+ Rb+ Rc)
b) Vio = Rmax/( Rmax+ Rb+ Rc)
c) Vio = (Rc*Vmax)/( Rmax+ Rb+ Rc)
d) Vio = Vmax/( Rmax+ Rb+ Rc)
Explanation: Compensating network using maximum Thevenin’s equivalent for resistance and voltage circuit is shown. Since |V1-V2|- Vio, the maximum value of V2 can be equal to Vio.

23. Find the value of Ra and Rb from the circuit shown?

a) Ra =4.6kΩ ; Rb= 9kΩ
b) Ra =7.3kΩ ; Rb= 3.4kΩ
c) Ra =2.5kΩ ; Rb= 5.1kΩ
d) Ra =4kΩ ; Rb= 10kΩ
Explanation: We know that input offset voltage, Vio =(Rc*Vmax)/ Rb
=> Rb = Vmax*(Rc / Rb ) = (10v/10mv)*10Ω (∵ Vio specified on the datasheet is 10mv for LM307 op-amp).
=> Rb =10000 = 10kΩ.
Since Rb > Rmax let us choose Rb = 10*Rmax. (Where Rmax = Ra/4).
∴ Rb = (10*Rb)/4 and Ra = Rb/2.5 = 10kΩ/2.5=4kΩ.

24. Why does an op-amp without feedback is not used in linear circuit application?
a) Due to high current gain
b) Due to high voltage gain
c) Due to high output signal
d) All of the mentioned
Explanation: In an op-amp without feedback, the voltage gain is extremely high (ideally infinite). Because of the high risk of distortion and clipping of the output signal, an op-amp in open loop configuration is not used in linear circuit application.

25. When the input voltage is reduced to zero in a closed-loop configuration the circuit acts as
a) Inverting amplifier
b) Non-inverting amplifier
c) Inverting and non-inverting amplifier
d) None of the mentioned
Explanation: Since the input signal voltage is reduced to zero, the internal resistance is negligibly small. The output offset voltage is expressed in terms of external resistance and the specified input offset voltage for a given op-amp.
If the non-inverting input terminal is connected to the ground, it acts as inverting op-amp and vice versa.

26. How the value of output offset voltage is reduced in closed-loop op-amp?
a) By increasing gain
b) By reducing gain
c) By decreasing bandwidth
d) By reducing bandwidth
Explanation: The output offset voltage is a product of gain and specified input offset voltage for a given op-amp. Voo= Aoo*Vio. So, the value of output offset voltage can be reduced by reducing the gain value.

27. What happens if R1>>RF in the circuit

a) Some amount of output offset voltage is present
b) Some amount of input offset voltage is present
c) Some amount of gain voltage is present
d) All of the mentioned
Explanation: If R1 >>RF, the gain Aoo≅1, which makes Voo ≅ Vio. Thus, all op-amp circuit has some output offset voltage.

28. Determine the voltage gain for the circuit.

a) 1.1
b) 1.6
c) 1.2
d) 2.2
Explanation: The voltage gain, AF={1+[RF/( R1+ Rc)]} = 1+[15kΩ/(2.5kΩ+10kΩ)] = 2.2.

29. Where does the compensating network connected in an inverting amplifier.
a) Non-inverting input terminal
b) Inverting input terminal
c) Between non-inverting and output terminal
d) Between inverting and output terminal
Explanation: The offset voltage compensating network is connected in the non-inverting terminal for the inverting amplifier and vice versa.

30. Why closed-loop differential amplifiers are difficult to null?
a) Due to compensating network
b) Due to feedback loop
c) Due to input offset voltage
d) None of the mentioned
Explanation: The closed loop differential amplifiers are more difficult to null because the use of compensating network can change the common mode rejection mode.

31. How to achieve maximum CMRR in the given circuit?

a) R1 = RF
b) RF = R3|| RC+ RB and R1= R2
c) R1= R2 and RF= R3+ RC
d) None of the mentioned
Explanation: To achieve maximum CMRR in the circuit the value of R1= R2 and RF= R3+ RC.

32. What is the advantage of compensated differential amplifier?
a) All of the mentioned
b) Slightly complex circuit
c) Does not affect CMRR
d) Balanced op-amp
Explanation: Since the compensated differential amplifier uses the op-amp with offset voltage null pins. The offset null circuit does not affect the CMRR.

33. The offset voltage in the voltage follower is balanced using
a) Voltage drop across the load resistor
b) Voltage drop across feedback resistor
c) Compensating network connected to inverting input terminal
d) Compensating network connected to non- inverting input terminal
Explanation: Voltage drop across the feedback resistor connect to inverting input terminal is used to cancel the offset voltage in voltage follower.

34. Find the maximum possible output offset voltage, which is caused by the input offset voltage Vio=15mv?

a) 0.075v
b) 0.75v
c) 0.75v
d) 7.5v
Explanation: Aoo=[1+(RF/R1)] =1+(10kΩ/2.5kΩ) = 5.
Voo=5*15mv = 75mv.

35. Compute the output voltage for voltage follower with offset voltage compensating network?

a) 3.6v
b) 10.8v
c) 26v
d) 33v
Explanation: The output voltage is given as Vo= {1+[ RC/( Rb+ (Rmax/4))]}*Vin.
Rmax=Ra/4 = 20kΩ/4 = 5kΩ.
Vo=[1+(39kΩ/(10kΩ+5kΩ))]*3v = 10.8v.

36. Input bias current is defined as
a) Average of two input bias current
b) Summing of two input bias current
c) Difference of two input bias current
d) Product of two input bias current
Explanation: Input bias current is the average of two input bias current flowing into the non-inverting and inverting input of an op-amp.

37. Although the value of input bias current is very small, it causes
a) Output voltage
b) Input offset voltage
c) Output offset voltage
d) All of the mentioned
Explanation: Even a very small value of input bias current can cause a significant output offset voltage in circuits using relatively large feedback resistors.

38. The formula for output offset voltage of an op-amp due to input bias current
a) VOIB= RF*IB
b) VOIB= (RF+R1)/IB
c) VOIB= (1+RF)*IB
d) VOIB= [1+(RF/R1)]*IB
Explanation: The output offset voltage due to input bias current is VOIB = RF*IB.

39. Find the input bias current for the circuit given below

a) 10mA
b) 2mA
c) 5mA
d) None of the mentioned
Explanation: Input bias current, IB=(IB1+ IB2)/2
=> IB =(4mA+6mA)/2 = 5mA.

40. Mention a step to reduce the output offset voltage caused due to input bias current?
a) Use small feedback resistor and resistance at the input terminal
b) Use small feedback resistors
c) Reduce the value of load resistors
d) None of the mentioned
Explanation: Since the output offset voltage is proportional to feedback resistor and input bias current. The amount of VOIB can be reduced by reducing the value of feedback resistor.

41. Given below is a differential amplifier in which V1=V2. What happens to VOIB at this condition?

a) VOIB= 0
b) VOIB= VOIB×10-10
c) VOIB= VOIB/2
d) VOIB= -1
Explanation: The voltage V1 and V2 are caused by the current IB1 and IB2. Although this bias current are very small, if they are made equal, then there will be no output voltage VOIB.

42. Name the resistor that is connected in the non-inverting terminal of op-amp which is in parallel combination of resistor connected in inverting terminal and feedback resistor.
a) Random minimizing resistor
b) Offset minimizing resistor
c) Offset reducing resistors
d) Output minimizing resistors
Explanation: The voltage is product of resistors and input bias current. Therefore, the value of the resistors are adjusted such that the resistors are connected at the inverting input terminal is made equal to resistor connected in non-inverting input terminal. The use of this resistors minimize the amount of output offset voltage and therefore, they are referred to as offset minimizing resistors.

43. Calculate ROM, if the value of IB1 = IB2 in the given circuit.

a) 1173.11Ω
b) 171.31Ω
c) 1171.43Ω
d) 1071.43Ω
Explanation: Offset minimizing resistor, ROM =(R1* RF)/( R1+RF).
=> ROM = (1.2kΩ*10kΩ)/(1.2kΩ+10Ω) = 1071.43Ω.

44. The circuit in which the output voltage waveform is the integral of the input voltage waveform is called
a) Integrator
b) Differentiator
c) Phase shift oscillator
d) Square wave generator
Explanation: Integrator circuit produces the output voltage waveform as the integral of the input voltage waveform.

45. Find the output voltage of the integrator
a) Vo = (1/R×CF)×t∫0 Vindt+C
b) Vo = (R/CF)×t∫0 Vindt+C
c) Vo = (CF/R)×t∫0 Vindt+C
d) Vo = (R×CF)×t∫0 Vindt+C
Explanation: The output voltage is directly proportional to the negative integral of the input voltage and inversely proportional to the time constant RCF.
Vo = (1/R×CF)×t∫0 Vindt+C
Where C-> Integration constant and CF-> Feedback capacitor.

46. Why an integrator cannot be made using low pass RC circuit?
a) It require large value of R and small value of C
b) It require large value of C and small value of R
c) It require large value of R and C
d) It require small value of R and C
Explanation: A simple low pass RC circuit can work as an integrator when time constant is very large, which require large value of R and C. Due to practical limitations , the R and C cannot be made infinitely large.

47. How a perfect integration is achieved in op-amp?
a) Infinite gain
b) Low input impedance
c) Low output impedance
d) High CMRR
Explanation: In an op-amp integrator the effective input capacitance becomes CF×(1-Av). Where Av is the gain of op-amp. The gain is infinite for ideal op-amp. So, effective time constant of the op-amp integrator becomes very large which results in perfect integration.

48. The op-amp operating in open loop result in output of the amplifier to saturate at a voltage
a) Close to op-amp positive power supply
b) Close to op-amp negative power supply
c) Close to op-amp positive or negative power supply
d) None of the mentioned
Explanation: In practice, the output of op-amp never becomes infinite rather the output of the op-amp saturate at a voltage close to op-amp positive or negative power supply depending on the polarity of the input dc signal.

49. The frequency at which gain is 0db for integrator is
a) f=1/(2πRFCF)
b) f=1/(2πR1CF)
c) f=1/(2πR1R1)
d) f=(1/2π)×(RF/R1)
Explanation: The frequency at which the gain of the integrator becomes zero is f=1/(2πR1CF).

50. Why practical integrator is called as lossy integrator?
a) Dissipation power
b) Provide stabilization
c) Changes input
d) None of the mentioned
Explanation: To avoid saturation problems, the feedback capacitor is shunted by a feedback resistance(RF). The parallel combination of RF and CF behave like a practical capacitor which dissipates power. For this reason, practical integrator is called as a lossy integrator.

51. Determine the lower frequency limit of integration for the circuit given below.

a) 43.43kHz
b) 4.82kHz
c) 429.9kHz
d) 4.6MHz
Explanation: The lower frequency limit of integration, f= 1/(2πRFCF) = 1/(2π×1kΩ×33nF) = 4.82kHz.

52. How is the higher order filters formed?
a) By increasing resistors and capacitors in low pass filter
b) By decreasing resistors and capacitors in low pass filter
c) By inter changing resistors and capacitors in low pass filter
d) All of the mentioned
Explanation: High pass filter are often formed by interchanging frequency determining resistors and capacitors in low pass filters. For example, a first order high pass filter is formed from a first order low pass filter by inter changing components Rand C.

53. In a first order high pass filter, frequencies higher than low cut-off frequencies are called
a) Stop band frequency
b) Pass band frequency
c) Centre band frequency
d) None of the mentioned
Explanation: Low cut-off frequency, fL is 0.707 times the pass band gain voltage. Therefore, frequencies above fL are pass band frequencies.

54. Compute the voltage gain for the following circuit with input frequency 1.5kHz.

a) 4dB
b) 15dB
c) 6dB
d) 12dB
Explanation: |VO/Vin|= [AF×(f/fL)]/ [√1+(f/fL)2] = [4×(1.5kHz/225.86)] / √[1+(1.5kHz/225.86)2] =26.56/6.716=3.955 =20log(3.955)=11.9.
|VO/Vin|≅12 dB
AF= 1+(RF /R1)= 1+(12kΩ/4kΩ) =4.
fL= 1/(2πRC) = 1/2π×15kΩ×0.047µF= 1/4.427×10-3 =225.86Hz.

55. Determine the expression for output voltage of first order high pass filter?
a) VO = [1+(RF /R1)]× [(j2πfRC/(1+j2πfRC)] × Vin
b) VO = [-(RF /R1)]× [(j2πfRC/(1+j2πfRC)] × Vin
c) VO = {[1+(RF /R1)]× /[1+j2πfRC] }× Vin
d) None of the mentioned
Explanation: The first order high pass filter uses non-inverting amplifier. So, AF= 1+(RF /R1) and the output voltage, VO = [1+(RF /R1)]× [(j2πfRC/(1+j2πfRC)]× Vin.

56. The internal resistor of the second order high pass filter is equal to 10kΩ. Find the value of feedback resistor?
a) 6.9kΩ
b) 5.86kΩ
c) 10kΩ
d) 12.56kΩ
Explanation: Pass band gain for second order butterworth response, AF =1.586.
=> AF= [1+(RF/R1)] => RF= (AF-1)×R1 =(1.586-1)×10kΩ =5860 =5.86kΩ.

57. Consider the following circuit and calculate the low cut-off frequency value?

a) 178.7Hz
b) 89.3Hz
c) 127.65Hz
d) 255.38Hz
Explanation: The low cut-off frequency for the given filter is fL =1/√[2π√(R2×R3×C2×C3)]=178.7Hz.

58. Determine voltage gain of second order high pass butterworth filter.
Specifications R3 =R2=33Ω, f=250hz and fL=1khz.
a) -11.78dB
b) -26.51dB
c) -44.19dB
d) None of the mentioned
Explanation: Since R3 =R2
=> C2 = 1/(2π ×fL×R2) = 1/(2π ×1kHz×33Ω)
=> C3 =C2= 4.82µF.
Voltage gain of filter |VO/Vin|=AF / [√ 1+(fL/f)4] = 1.586/[1+(1kHz/250kz)4] =1.586/252=6.17×10-3 =20log(6.17×10-3)= -44.19dB.

59. From the given specifications, determine the value of voltage gain magnitude of first order and second order high pass butterworth filter?
Pass band voltage gain=2;
Low cut-off frequency= 1kHz;
Input frequency=500Hz.
a) First order high pass filter =-4.22dB , Second order high pass filter=-0.011dB
b) First order high pass filter =-0.9688dB , Second order high pass filter=-6.28dB
c) First order high pass filter =-11.3194dB , Second order high pass filter=-9.3257dB
d) First order high pass filter =-7.511dB , Second order high pass filter=-5.8999dB
Explanation: For first order high pass filter,
|VO/Vin|=AF ×(f/fL) / [ √1+(f/fL)2] =(2×(500Hz/1kHz)) /√[1+(500Hz/1kHz)2] => |VO/Vin| = 1/1.118= 0.8944 =20log(0.8944) =-0.9686dB.
For second order high pass filter,
|VO/Vin|=AF / [ √ 1 +(fL/f)4] =2/√[1+ (1kHz/500Hz)2] =>|VO/Vin|=2/4.123= =0.4851 = 20log(0.4851) = -6.28dB.

60. How is the higher order filters formed?
a) Using first order filter
b) Using second order filter
c) Connecting first and second order filter in series
d) Connecting first and second order filter in parallel
Explanation: Higher filters are formed by using the first and second order filters. For example, a third order low pass filter is formed by cascading first and second order low pass filter.

61. State the disadvantage of using higher order filters?
a) Complexity
b) Requires more space
c) Expensive
d) All of the mentioned
Explanation: Although higher order filter than necessary gives a better stop band response, the higher order type is more complex, occupies more space and is more expensive.

62. The overall gain of higher order filter is
a) Varying
b) Fixed
c) Random
d) None of the mentioned
Explanation: The overall gain of higher order filter is fixed because all the frequency determining resistor and capacitors are equal.

63. Find the roll-off rate for 8th order filter
Explanation: For nth order filter the roll-off rate will be -n×20dB/decade.
=>∴ for 8th order filter= 8×20=160dB/decade.

64. Which filter attenuates any frequency outside the pass band?
a) Band-pass filter
b) Band-reject filter
c) Band-stop filter
d) All of the mentioned
Explanation: A band- pass filter has a pass band between two cut-off frequencies fH and fL. So, any frequency outside this pass band is attenuated.

65. Narrow band-pass filters are defined as
a) Q < 10
b) Q = 10
c) Q > 10
d) None of the mentioned
Explanation: Quality factor (Q) is the measure of selectivity, meaning higher the value of Q, the narrower its bandwidth.

66. A band-pass filter has a bandwidth of 250Hz and center frequency of 866Hz. Find the quality factor of the filter?
a) 3.46
b) 6.42
c) 4.84
d) None of the mentioned
Explanation: Quality factor of band-pass filter, Q =fc/bandwidth= 566/250=3.46.

67. Find the center frequency of wide band-pass filter
a) fc= √(fh ×fL)
b) fc= √(fh +fL)
c) fc= √(fh -fL)
d) fc= √(fh /fL)
Explanation: In a wide band-pass filter, the product of high and low cut-off frequency is equal to the square of center frequency
i.e. ( fc)2 =fH×fL
=> fc= √(fh×fL).

68. Find out the voltage gain magnitude equation for the wide band-pass filter.
a) AFt×( f/fL)/√[(1+(f/fh)2]×[1+(f/fL)2].
b) AFt/ √{[1+(f/fh)2]×[1+(f/fL)2]}
c) AFt/ √{[1+(f/fh)2]/[1+(f/fL)2]}
d) [AFt/(f/fL)]/ √{[1+(f/fh)2]/[1+(f/fL)2]}
Explanation: The voltage gain magnitude of the band-pass filters equal to the product of the voltage gain magnitudes of high pass and low pass filter.

69. When a second order high pass filter and second order low pass sections are cascaded, the resultant filter is a
d) None of the mentioned
Explanation: The order of the band-pass filter depends on the order of the high pass and low pass filter sections.

70. Find the voltage gain magnitude of the wide band-pass filter?
Where total pass band gain is=6, input frequency = 750Hz, Low cut-off frequency =200Hz and
high cut-off frequency=1khz.
a) 13.36 dB
b) 12.25 dB
c) 11.71 dB
c) 14.837dB
Explanation: Voltage gain of the filter,
|VO/Vin|=[AFt×(f/fL)]/{√[1+(f/fL)2]×[1+f/fL)2]} =[6×(750/20)]/√{[1+(750/200)2]×[1+(750/200)2]}
=22.5/√(15.6×1.56) =5.519.
|VO/Vin|= 20log(5.519) =14.837dB.

71. Compute the quality factor of the wide band-pass filter with high and low cut-off frequencies equal to 950Hz and 250Hz.
a) 0.278
b) 0.348
c) 0.696
d) 0.994
Explanation: Quality factor Q=√(fh×fL)/(fh-fL) = √(950Hz×250Hz)/(9950Hz-250Hz) =0.696.

72. The details of low pass filter sections are given as fh =10kHz, AF= 2 and f=1.2kHz. Find the voltage gain magnitude of first order wide band-pass filter, if the voltage gain magnitude of high pass filter section is 8.32dB.
a) 48.13dB
b) 10.02dB
c) 14.28dB
d) 65.99dB
Explanation: |VO/Vin|(high pass filter) = 8.32dB=10(8.32/20) =2.606.
Therefore, the voltage gain of wide band-pass filter |VO/Vin|= AFt×(f/fL)/√[1+(f/fh)2)]×[1+(f/fL)2)] ={Af/√[(1+(f/fh)2]}×{(Af×f/fL)/√[1+(f/fL)2]} =Aft /√[1+(f/fh)2]×(2.606)
= [2/√(1+(1.2kHz/10kHz)2]×( 2.606) = 1.986×2.606 =5.17 =20log×(5.17) =14.28dB.

73. The quality factor of a wide band-pass filter can be
a) 12.6
b) 9.1
c) 14.2
d) 10.9
Explanation: A wide band-pass filter has quality factor less than 10.

74. Design a narrow band-pass filter, with fc=1kHz, Q= 13 and AF=10 (Take C=0.1µF)

Explanation: Given C =0.1µF.
Therefore, C1=C2 =0.1µF.
R1 =Q/(2π×fc×CAF) =13/( 2π×1kHz×0.1µF×10) =13/6.28 = 2.07 ≅ 2Ω.
R2 =Q/{2π×fc×C ×[(2Q2)- AF]} =13/{(2π×1kHz×0.1µF×[2×(132)-10]} = 13/0.2059=63.11 ≅ 63Ω.
R3 =Q/(π×fc×C) = 13/(π×1kHz×0.1µF) = 13/3.14×10-4 =41.40kΩ ≅41kΩ.

75. If the gain at center frequency is 10, find the quality factor of narrow band-pass filter
a) 1
b) 2
c) 3
d) None of the mentioned
Explanation: The gain of the narrow band-pass filter must satisfy the condition, AF= 2×Q2
When Q=3,
=> 2×Q2 =2×(32) =18.
=> 10<18. Hence condition is satisfied when Q=3.

76. The advantage of narrow band-pass filter is
a) fc can be changed without changing gain
b) fc can be changed without changing bandwidth
c) fc can be changed without changing resistors
d) All of the mentioned
Explanation: As the narrow band-pass filter has multiple filters. The center frequency can be changed to a new frequency without changing the gain or bandwidth and is accomplished by changing the resistor to a new value which is given as
R’=R×(fL/fc)2.

#### Module 3

1. How are the square wave output generated in op-amp?
a) Op-amp is forced to operate in the positive saturation region
b) Op-amp is forced to operate in the negative saturation region
c) Op-amp is forced to operate between positive and negative saturation region
d) None of the mentioned
Explanation: Square wave outputs are generated where the op-amp is forced to operate in saturated region, that is, the output of the op-amp is forced to swing repetitively between positive saturation, +Vsat and negative saturation, -Vsat.

2. The following circuit represents a square wave generator. Determine its output voltage

a) -13 v
b) +13 v
c) ± 13 v
d) None of the mentioned
Explanation: The differential output voltage Vid = Vin1 – Vin2= 3-7v = -4v.
The output of the op-amp in this circuit depends on polarity of differential voltage V0= -Vsat ≅ -Vee = -13 v.

3. Determine the expression for time period of a square wave generator
a) T= 2RC ln×[( R1+ R2) / ( R2)].
b) T= 2RC ln×[( 2R1+ R2) / ( R2)].
c) T= 2RC ln×[( R1+ 2R2) / ( R2)].
d) T= 2RC ln×[( R1+ R2) / (2 R2)].
Explanation: The time period of the output waveform for a square wave generator is T= 2RC ln×[(2R1+ R2)/( R2)].

4. Determine capacitor voltage waveform for the circuit

Explanation: When the op-amp output voltage is at negative saturation, V1 = [(R1) / (R1+ R2 )] × (-Vsat) = [10kΩ / ( 10 kΩ +11.6 kΩ)] × (-15v) = -7v.
Similarly, when the op-amp’s output voltage is at positive saturation, V1 = [(R1) / (R1+ R2 )] × (+Vsat) = [10kΩ/ ( 10 kΩ +11.6 kΩ)] × (+15v) = +7v
The time period of the output waveform,T= 2RC ln ×[( 2R1+ R2) / ( R2)] = 2× 10kΩ × 0.05 µF× ln (2×10kΩ + 11.6kΩ) / 11.6kΩ] = 1×10-3 × ln2.724 = 1ms.
The voltage across the capacitor will be a triangular wave form.

5. What will be the frequency of output waveform of a square wave generator if R2 = 1.16 R1?
a) fo = (1/2RC)
b) fo = (ln/2RC)
c) fo = (ln /2 ×√RC)
d) fo = (ln/√(2 RC))
Explanation: When R2= 1.16 R1, then fo = 1/2RC× ln[ (2R1+ R2) / R2] = 1/2RC ×ln [(2R1 + 1.161R1 )/ (1.161R1)] = 1/( 2RC×ln2.700)= 1/2RC.

6. What could be the possible output waveform for a free running multivibrator whose op-amp has a supply voltage of ±5v operating at 5khz?

Explanation: In a free running multivibrator, the output is forced to swing repetitively between positive and negative saturation to produce square wave output. Therefore, +Vsat ≅ +Vcc =+5v and -Vsat ≅ -Vcc =-5v.
=> Frequency= 5khz , f =1/t = 0.2ms.

7. Determine the output frequency for the circuit given below

a) 28.77 Hz
b) 31.97 Hz
c) 35.52 Hz
d) 39.47 Hz
Explanation: The output frequency fo = 1/2RC×ln [ (2R1+ R2)/ R2] = 1 / {(2×33kΩ ×0.33µF)×ln[(2×33kΩ +30kΩ)/30kΩ]} = 1/ (0.02175×ln 32) = 39.47 Hz.

8. The value of series resistance in the square wave generator should be 100kΩ or higher in order to
a) Prevent excessive differential current flow
b) Increase resistivity of the circuit
c) Reduce output offset voltage
d) All of the mentioned
Explanation: In practice, each inverting and non-inverting terminal needs a series resistance to prevent excessive differential current flow because the inputs of the op-amp are subjected to large differential voltages.

9. Why zener diode is used at the output terminal of square wave generator?
a) To reduce both output and capacitor voltage swing
b) To reduce output voltage swing
c) To reduce input voltage swing
d) To reduce capacitor voltage swing
Explanation: A reduced peak-peak output voltage swing can be obtained in the square wave generator by using back to back zener diodes at the output terminal.

10. A square wave oscillator has fo =1khz. Assume the resistor value to be 10kΩ and find the capacitor value?
a) 3.9 µF
b) 0.3 µF
c) 2 µF
d) 0.05µF
Explanation: Let’s take R2 = 1.16 R2, therefore the output frequency fo = 1/2RC
=> C = 1/2Rfo = 1/ (2×10kΩ×1khz) = 0.05µF.

11. How a triangular wave generator is derived from square wave generator?
a) Connect oscillator at the output
b) Connect Voltage follower at the output
c) Connect differential at the output
d) Connect integrator at the output
Explanation: The output waveform of the integrator is triangular, if its input is square wave. Therefore, a triangular wave generator can be obtained by connecting an integrator at the output of the square wave generator.

12. The increase in the frequency of triangular wave generator.
a) Ramp the amplitude of triangular wave
b) Increase the amplitude of triangular wave
c) Decrease the amplitude of triangular wave
d) None of the mentioned
Explanation: As the resistor value increase or decrease, the frequency of triangular wave will decrease or increase, respectively. Therefore, the amplitude of the triangular wave decreases with an increase in it frequency and vice verse.

13. Which among the following op-amp is chosen for generating triangular wave of relatively higher frequency?
a) LM741 op-amp
b) LM301 op-amp
c) LM1458 op-amp
d) LM3530 op-amp
Explanation: The frequency of the triangular wave generator is limited by the slew rate of the op-amp. LM301 op-amp has a high slew rate.

14. What is the peak to peak (PP) output amplitude of the triangular wave?
a) VO(pp) = + VRamp + (- VRamp)
b) VO(pp) = – VRamp + (+ VRamp)
c) VO(pp) = + VRamp – (- VRamp)
d) VO(pp) = – VRamp – (+ VRamp)
Explanation: The peak to peak output waveform, VO(pp) = + VRamp-(-VRamp)
Where, – VRamp –> Negative going ramp ;
+ VRamp–> positive going ramp.

15. Determine the output triangular waveform for the circuit.

Explanation: The voltage at which A1 switch from +Vsat to -Vsat
=> -Vramp =(-R2 / R3) × (+Vsat)
= (-10kΩ/40kΩ) ×15v =-3.75v
Similarly, the voltage at which A1 switch from -Vsat to +Vsat
=> +Vramp = (-R2 / R3) × (-Vsat)
= 10kΩ/40kΩ ×15v =3.75v
∴ Time period, T = (4R1C1R2) / R3
= (4×10kΩ×0.05µF×10kΩ) /40kΩ = 0.5 ms.

16. Find the capacitor value for a the output frequency, fo = 2kHz & VO(pp) = 7v , in a triangular wave generator. The op-amp is 1458/741 and supply voltage = ±15v. (Take internal resistor=10kΩ)
a) 0.03nF
b) 30nF
c) 0.3nF
d) 3nF
Explanation: Given, Vsat =15v
∴ VO(pp) = (2R2/R3) × Vsat
=> R2 =(VO(pp) ×R3) / (Vsat×2) = [7/(2×15)]×R3 = 0.233R3
∵ Internal resistor, R2 = R1= 10kΩ
=> R3 = 0.233×10kΩ = 2.33kΩ.
So, the output frequency fO = R3 / ( 4×R1 ×C1× R2)
=> 2khz = 2.33khz/ (4×10kΩ ×10kΩ×C1)
=> C1 = 2.33kΩ / (8×10-11) = 2.9 ×10-9 ≅3nF.

17. Triangular wave form has
a) Rise time < fall time
b) Rise time = fall time
c) Rise time ≥ fall time
d) None of the mentioned
Explanation: The triangular wave form has rise time of the triangular wave always equal to its fall time, that is, the same amount of time is required for the triangular wave to swing from -VRamp to +VRamp as from +VRamp to -VRamp.

18. Output of an integrator producing waveforms of unequal rise and fall time are called
a) Triangular waveform
b) Sawtooth waveform
c) Pulsating waveform
d) Spiked waveform
Explanation: Sawtooth waveform has unequal rise and fall times. It may rise positively many times faster than it falls negatively or vice versa.

19. Find out the sawtooth wave generator from the following circuits.

Explanation: The triangular wave generator can be converted into a sawtooth wave generator by inserting a variable dc voltage into the non-inverting terminal of the integrator.

20. Which circuit converts irregularly shaped waveform to regular shaped waveforms?
a) Schmitt trigger
b) Voltage limiter
c) Comparator
d) None of the mentioned
Explanation: Schmitt trigger are also called as squaring circuit because, this type of circuit converts an irregularly shaped wave to a square wave or pulse.

21. Determine the upper and lower threshold voltage

a) VUT = +14.63v, VLT= +14.63v
b) VUT = -14.63v, VLT= -14.63v
c) VUT = VLT= ±14.63v
d) None of the mentioned
Explanation: Upper threshold voltage, VUT = [R1/(R1+ R2)]× (+Vsat) = [10kΩ/(10kΩ +250Ω)]×(+15v)= +14.63v.
Lower threshold voltage VLT = [R1/(R1+ R2)]×( -Vsat) = [10kΩ /(10kΩ+250Ω)]×(-15v)= -14.63v.

22. What happens if the threshold voltages are made longer than the noise voltages in schmitt trigger?
a) All the mentioned
b) Enhance the output signal
c) Reduce the transition effect
d) Eliminate false output transition
Explanation: In schmitt trigger, if the threshold voltage VUT and VLT are made larger than the input noise voltage. The positive feedback will eliminate the false output transition.

23. To a schmitt trigger in non-inverting configuration an input triangular wave of 1Vp is applied. What will be the output waveform, if the upper and lower threshold voltages are 0.25v?
a) Square waveform
b) Pulse waveform
c) Sawtooth waveform
d) Cannot be determined
Explanation: The input waveform has a threshold level of ±0.25v.

24. In which configuration a dead band condition occurs in schmitt trigger
a) Differential amplifier with positive feedback
b) Voltage follower with positive feedback
c) Comparator with positive feedback
d) None of the mentioned
Explanation: The comparator with positive feedback is said to exhibit hysteresis, a dead band condition, when the input of comparator exceeds upper threshold voltage. At this condition, output switch from +Vsat to -Vsat. It reverts back to its original state, +Vsat when the input goes below lower threshold voltage.

25. Calculate the hysteresis voltage for the schmitt trigger from the given specification:
R2 =56kΩ , R1 = 100Ω ,Vref = 0v & Vsat = ±14v.

a) 0 mv
b) 25 mv
c) 50 mv
d) -25 mv
Explanation: Upper threshold voltage, VUT =[R1/(R1+R2)]×( +Vsat) = [100kΩ/(56kΩ +100 Ω)]×(+14v)= +25mv.
Lower threshold voltage VLT = [R1/(R1+ R2)]×(-Vsat) = [100kΩ /(56kΩ+100Ω)]×(-14v)= -25 mv.
∴ Hysteresis voltage = VUT-VLT = 25-(-25) = 50mv.

26. How to limit the output voltage swing only to positive direction?
a) Combination of two zener diodes
b) Combination of zener and rectifier diode
c) All of the mentioned
d) Combination of two rectifier diodes
Explanation: To limit the output voltage swing to positive or negative direction, the basic op-amp comparator should be connected with a combination of zener and rectifier diode in the feedback path.

27. For the circuit shown below, obtain output waveform. Assume zener voltage to be 4.78v and voltage drop across the forward biased zener to be 0.7v.

Explanation: During positive half cycle of the input waveform, the output voltage is equal to (VZ +VD1) (because diode D1 would be in forward bias) ,
∴ (VZ +VD1) = 4.78 v+0.7 v = 5.5 v.
Similarly, during negative half cycle of the input wave form, the output voltage is equal to – (VZ +VD2) as the diode D2 would be in forward bias) , – (VZ +VD2) =- 4.78 v-0.7 v = -5.5 v.

28. A basic op-amp circuit has a zener and rectifier diode connected in the feedback path. Calculate the maximum positive voltage. Where, zener voltage = 5.1 v and voltage drop across the forward biased zener = 0.7v?
a) VO = 5.8v
b) VO = 9.9v
c) VO = 4.7v
d) VO = 7.1v
Explanation: Initially, rectifier diode will be reverse biased and makes the op-amp to operate in open loop configuration. So, the output voltage is obtained till the rectifier diode is forward bias and zener goes into avalanche condition. Hence, the maximum positive output voltage VOz +VD (VD –> voltage drop across rectifier diode).
=> VO= 5.1v+0.7 v= 5.8v.

29. Use the specification and obtain the output voltage swing for op-amp comparator.
Specification: R= 1kΩ; RL=10kΩ; VZ=6v; VSat=±15v (Assume forward bias of zener = 0.7v).

Explanation: During the positive half cycle, the output voltage would be at -VD = -0.7v because the zener will be forward biased. However, during negative half cycle of VO would be at +VZ =+6v. Thus, the zener diode in the feedback path limits VO to swing between +6v to -0.7v.

30. Depending on the value of input and reference voltage a comparator can be named as
a) Voltage follower
b) Digital to analog converter
c) Schmitt trigger
d) Voltage level detector
Explanation: A comparator is some time called as voltage level detector because, for a desired value of reference voltage, the voltage level of the input can be detected.

31. Why clamp diodes are used in comparator?
a) To reduce output offset voltage
b) To increase gain of op-amp
c) To reduce input offset current
d) To protect op-amp from damage
Explanation: The diodes protect the op-amp from damage due to excessive input voltage. Because of these diodes the difference input voltage of the op-amp is clamped to 0.7v or -0.7 v, hence these diodes are clamp diodes.

32. Find the non-inverting comparator

Explanation: In a non-inverting comparator a fixed reference voltage Vref of 1v is applied to positive inverting input terminal and the other time vary in signal voltage is applied to non-inverting input terminal of the op-amp.

33. How the op-amp comparator should be choosen to get higher speed of operation?
a) Large gain
b) High slew rate
c) Wider bandwidth
d) None of the mentioned
Explanation: The bandwidth of the op-amp comparator must be wider so that the output of comparator can switch rapidly between saturation levels. Also, the op-amp responds instantly to any change in condition at the input.

34. How to obtain high rate of accuracy in comparator?
a) Input offset
b) High voltage gain
c) High CMRR
d) All of the mentioned
Explanation: High voltage gain causes comparator output voltage to switch between saturation levels. High CMRR rejects noise at input terminal and input offset (voltage & current) help to keep changes in temperature variation very slight.

35. How to keep the output voltage swing of the op-amp comparator within specific limits?
a) External resistors or diodes are used
b) External zeners or diodes are used
c) External capacitors or diodes are used
d) External inductors or diodes are used
Explanation: To keep the output voltage swing within specific limit, op-amps are used with external wired components such as zeners or diodes. In the resulting circuit, the outputs are limited to predetermined values.

36. Zero crossing detectors is also called as
a) Square to sine wave generator
b) Sine to square wave generator
c) Sine to triangular wave generator
d) All of the mentioned
Explanation: In zero crossing detectors, the output waveform is always a square wave for the applied sinusoidal input signal.

37. What is the drawback in zero crossing detectors?
a) Low frequency signal and noise at output terminal
b) High frequency signal and noise at input terminal
c) Low frequency signal and noise at input terminal
d) High frequency signal and noise at output terminal
Explanation: Due to low frequency signal, the output voltage may not switch quickly from one saturation voltage to other. The presence of noise can fluctuate the output between two saturation voltages.

38. State a method to overcome the drawback of zero crossing detectors?
a) Increasing input voltage
b) Use of positive feedback
c) Connect a compensating network
d) None of the mentioned
Explanation: The drawback of zero crossing detectors can be in cured with the use of regenerative or positive feedback that causes the output to change faster and eliminate any false output transition due to noise signals at the input.

39. Name the comparator that helps to find unknown input.
a) Time marker generator
b) Zero crossing detectors
c) Phase meter
d) Window detector
Explanation: Sometimes it is necessary to find the instant at which an unknown input is between two threshold levels. This can be achieved by a circuit called window detector.

40. Find the instance at which the input can be fed to the op-amp in a three level comparator with LED indicator.

a) When Green LED glow
b) When Yellow LED glow
c) When Red LED glow
d) All of the mentioned
Explanation: The input can be fed to the op-amp when the green LED glows, which is considered to be safe input that is when the input voltage is between 3v and 6v.

41. Find the output voltage at the point V2 from the given circuit.

Explanation: The output of the zero crossing detector is differentiated by an RC circuit (RC>>1). So, the voltage at V2 is a series of positive and negative pulses.

42. Mention the application areas of time marker generator can be used
a) Monoshots
b) SCR
c) Sweep voltage of CRT
d) All of the mentioned

Explanation: A diode connected at the output of time marker generator circuit converts the sinusoidal signal into a train of positive pulses. So, these pulses are used in triggering the monoshot, SCR, sweep voltage of CRT, etc.

43. Which among the following is used to increase phase angle between different voltages?
a) Phase detector
b) Window detector
c) Zero crossing detector
d) None of the mentioned

Explanation: Phase angle between different voltages can be measured using phase detector circuit. The corresponding voltage to be measured is converted into spikes and the time interval between the pulse spikes is measured, which is proportional to the phase difference.

44. For the comparator shown below, determine the transfer curves if an ideal op-amp with VZ1= VZ2=9v.

Explanation: The open-loop voltage gain of an ideal op-amp AOl=∞, even a small positive or negative voltage at the input drives the output to ±Vsat. So, the output voltage VO = ±( V2 +Vsat)
Therefore, VO = ±(VZ+VSat) =± (9+0.7) = ±9.7 v.

45. Which circuit can be used as a full wave rectifier?
a) Absolute vale output circuit
b) Positive clipper with two diodes
c) Negative clipper with two diodes
d) Peak clampers
Explanation: Absolute value output circuit produces an output signal that swings positively only, regardless of the polarity of the input signal; because of the nature of its output wave form, the circuit is used as full wave rectifier.

46. For the circuit shown below find the output voltage

a) Vo (+) = +10 v
b) Vo (+) = +12v
c) Vo (+) = +7v
d) None of the mentioned
Explanation: The voltage at the terminal V1 = (Vp -Vd1) /2
V1 = (12-0.7) /2 = 5.65 v (Vd1= voltage drop across diode=0.7)
Similarly, the voltage at the negative terminal V2 = (Vo -Vd3 ) /2 = (Vo – 0.7) /2
Since Vid ≅ 0v , ∴ V1 = V2
Vo = (5.65 *2 ) + 0.7 = 12v.

47. Determine the output waveform for the circuit

Where input = 2 Vp sine wave with time period 0.2ms.

Explanation: Given circuit is the thevenin equivalent of absolute value output circuit. Therefore, the output will be equal to the input regardless of polarity.
Therefore, Vo (+) = Vo (-) = 2 Vp sine wave with 0.2 ms time period. So, the output wave form will be a full wave rectified output of 2v amplitude,

48. What is the alternate method to measure the values of non-sinusoidal waveform other than ac voltmeter?
a) Clipper
b) Clamper
c) Peak detector
d) Comparator
Explanation: A conventional ac voltmeter is designed to measure rms value of the pure sine wave whereas, the peak value of the non-sinusoidal wave forms can be a peak detector.

49. State the condition needed to be satisfied by peak detector for proper operation of circuit.
a) CRd ≤ T/10 and CRL ≥ 10T
b) CRd ≤ 10T and CRL ≥ T/10
c) CRd ≥ T/10 and CRL ≤ 10T
d) CRd ≥ 10T and CRL ≤ T/10
Explanation: For proper operation of the circuit, charging and discharging time constant must satisfy the following: CRd ≤ T/10 and CRL ≥ to 10T.

50. The resistor in the peak detector are used to
a) To maintain proper operation
b) Protect op-amp from damage
c) To get shaped non-sinusoidal waveform
d) None of the mentioned
Explanation: The resistor is used to protect the op-amp against the excessive discharge current, especially when the power supply is switched off.

51. How the recovery time of the op-amp is reduced?
a) Diode is connected at the output of amplifier
c) Forward biased diode resistor
d) Discharge capacitor
Explanation: The diode connected at the output of op-amp conducts during negative half cycle of input voltage. Hence, prevent the op-amp from going into negative saturation. This in turn helps to reduce the recovery time of the op-amp.

52. How to detect the negative peaks of input signals in the peak detector given below?

a) Reversing D1 diode
b) Reversing D1 and D2 diodes
c) Reversing D2 diode
d) Charging the positions of D1 and D2
Explanation: The negative peaks of the input signal Vin can be detected by reversing diodes D1 and D2.

53. In the sample and hold circuit, the period during which the voltage across capacitor is equal to input voltage
a) Sample period
b) Hold period
c) Delay period
d) Charging period
Explanation: The time periods of the sample and hold control voltage during which the voltage across capacitor is equal to the input voltage are called sample period.

54. During which period the op-amps output of sample and hold circuits is processed?
a) Delay period
b) Sample and hold period
c) Sample period
d) Hold period
Explanation: Hold period is the period during which the voltage across the capacitor is constant and the output of the op-amp is processed or observed during hold periods.

55. Which IC is mostly preferred for sample and hold circuit?
a) µ771
b) IC741
c) LF398
d) µ351
Explanation: LF398 have significant reduction in size and improved performance and require only an external storage capacitor.

56. Sample and hold circuit are used in
a) Analog to Digital modulation
b) Digital to analog modulation
c) Pulse position modulation
d) All of the mentioned
Explanation: All types of modulation involve taking samples of an input signal and hold on to it last sample value until the input is sampled.

#### Module 4

1. Determine the time period of a monostable 555 multivibrator.
a) T = 0.33RC
b) T = 1.1RC
c) T = 3RC
d) T = RC
Explanation: The time period of a monostable 555 timer is T = RC×ln(1/3) = 1.1.RC.

2. Find monostable vibrator circuit using 555 timer.

Explanation: When 555 timer is configured in monostable operation, the trigger input is applied through pin2 whereas, upper comparator threshold (pin6) & discharge (pin7) are shorted and connected at the output.

3. How to overcome mistriggering on the positive pulse edges in the monostable circuit?
a) Connect a RC network at the input
b) Connect an integrator at the input
c) Connect a differentiator at the input
d) Connect a diode at the input
Explanation: To prevent the mistrigger on positive pulse edges, a resister & capacitor combined of 10kΩ and 0.001µF at the input to form a differentiator

The circuit shows the differentiator to be connected between trigger input and the +VCC.

4. A monostable multivibrator has R = 120kΩ and the time delay T = 1000ms, calculate the value of C?
a) 0.9µF
b) 1.32µF
c) 7.5µF
d) 2.49µF
Explanation: Time delay for a monostable multivibrator, T = 1.1RC
=> C = T/(1.1R) = 1000ms/(1.1×120kΩ) = 7.57µF.

5. Which among the following can be used to detect the missing heart beat?
a) Monostable multivibrator
b) Astable multivibrator
c) Schmitt trigger
d) None of the mentioned
Explanation: A monostable multivibrator can be used as a missing pulse detector by connecting a transistor between trigger inputs. If a pulse misses, the discharge trigger input goes high & transistor become cut-off and the output goes low. So, this type of circuit can be used to detect missing heart beat.

6. A 555 timer in monostable application mode can be used for
a) Pulse position modulation
b) Frequency shift keying
c) Speed control and measurement
d) Digital phase detector
Explanation: In monostable operation mode, if input trigger pulses are generated from a rotating wheel, the circuit will determine the wheel speed whenever it drops below a predetermined value. Therefore, it can be used for speed control and measurement.

7. How can a monostable multivibrator be modified into a linear ramp generator?
a) Connect a constant current source to trigger input
b) Connect a constant current source to trigger output
c) Replace resistor by constant current source
d) Replace capacitor by constant current source
Explanation: The resistor R of the monostable circuit is replaced by a constant current source. So, that the capacitor is charged linearly and generates ramp signal.

8. Determine time period of linear ramp generator using the specifications
RE = 2.7kΩ, R1 =47kΩ , R2 100kΩ , C= 0.1µF, VCC =5v.

a) 8ms
b) 4ms
c) 2ms
d) 1ms
Explanation: The time period of the linear ramp generator, T= [(2/3)×(VCC×RE)×(R1+ R2)×C]/{(R1×VCC)-[VBE×(R1+R2)]}
= {(2/3)×5v×[2.7kΩ×(4.7kΩ+ 100kΩ)]×(0.1µF)}/{[(47kΩ)×5v]-[(0.7)×(47kΩ+100kΩ)]}
=>T= 132.3/132.100 =1.0015×10-3 = 1ms.

9. What will be the output, if a modulating input signal and continuous triggering signal are applied to pin5 and pin22 respectively in the following circuit?

a) Frequency modulated wave form
b) Pulse width modulated wave form
c) Both pulse and frequency modulated wave form
d) None of the mentioned
Explanation: On application of continuous trigger at pin22 and a modulated input signal at pin5, a series of output pulses are obtained. The duration of which depends on the modulating signal. Also in the pulse duration, only the duty cycle varies, keeping the frequency same as that of the continuous input pulse train trigger.

10. Free running frequency of Astable multivibrator?
a) f=1.45/(RA+2RB)C
b) f=1.45(RA+2RB)C
c) f=1.45C/(RA+2RB)
d) f=1.45 RA/( RA+RB)
Explanation: The frequency of the Astable multivibrator is T=0.69(RA+2RB)C.
Therefore, f = 1/T =1.45/(RA+2RB)C.

11. Find the charging and discharging time of 0.5µF capacitor.

a) Charging time=2ms; Discharging time=5ms
b) Charging time=5ms; Discharging time=2ms
c) Charging time=3ms; Discharging time=5ms
d) Charging time=5ms; Discharging time=3ms
Explanation: The time required to charge the capacitor is tHigh=0.69(RA+RB)C =0.69(10kΩ+5kΩ)x0.5µF =5ms.
The time required to discharge the capacitor is tLow=0.69xRC =0.69x5kΩx0.5µF=2ms.

12. Astable multivibrator operating at 150Hz has a discharge time of 2.5m. Find the duty cycle of the circuit.
a) 50%
b) 75%
c) 95.99%
d) 37.5%
Explanation: Given f=150Hz.Therefore,T=1/f =1/150 =6.67ms.
∴ Duty cycle, D%=(tLow/T) x 100% = (2.5ms/6.67ms)x100% = 37.5%.

13. Determine the frequency and duty cycle of a rectangular wave generator.

a) Frequency=63.7kHz; Duty cycle=50%
b) Frequency=53.7kHz; Duty cycle=55%
c) Frequency=43.7kHz; Duty cycle=50%
d) Frequency=60kHz; Duty cycle=55%
Explanation: Frequency=1.45/(RA+RB)C .
Where RA=100Ω+50Ω=150Ω,
RB=100Ω+20Ω=120Ω.
=>∴f=1.45/((150+120)x0.1µF) = 53703Hz = 53.7kHz.
Duty cycle, D% = [RB/(RA+RB)] x 100% = 120Ω/(150Ω +120Ω) x 100% = 0.55×100% = 55%.

14. How to achieve 50% duty cycle in adjustable rectangular wave generator? (Assume R1 –> Resistor connected between supply and discharge and R2 –> Resistor connected between discharge and trigger input.)
a) R1 < R2
b) R1 > R2
c) R1 = R2
d) R1 ≥ R2
Explanation: The equation of duty cycle, D = R2/(R1 + R2). If R1 is made equal to R2 then 50% duty cycle is achieved.

15. How to obtain symmetrical waveform in Astable multivibrator?
a) Use clocked RS flip-flop
b) Use clocked JK flip-flop
c) Use clocked D-flip-flop
d) Use clocked T-flip-flop
Explanation: Symmetrical square wave can be obtained by adding a clocked JK flip-flop to the output of Astable multivibrator. The clocked flip-flop acts as a binary divider to the times output and produces 50% duty cycle without any restriction on the choice of resistors.

16. Determine the output frequency of the circuit.

a) 1450Hz
b) 1333Hz
c) 1871Hz
d) 1700Hz
Explanation: The output frequency of the frequency shift keying generator is
f=1.45/[(RA||RC)+2(RB)]xC = 1.45/[(2.3kΩ||2.3kΩ) + (2×3.3kΩ)] x 0.1µF = 1.45/{[(2.3×2.3)/(2.3+2.3)] + 6.6kΩ}x0.1µF = 1.45/(7.75×10-4) = 1870.9 ≅ 1871Hz.

17. How does a monostable multivibrator used as frequency divider?
a) Using square wave generator
b) Using triangular wave generator
c) Using sawtooth wave generator
d) Using sine wave generator
Explanation: Monostable multivibrator can be used as a frequency divider when a continuously triggered monostable circuit is triggered using a square wave generator. Provided the timing interval is adjusted to be longer than the period of triggering square wave input signal.

18.Pulse stretching, time-delay, and pulse generation are all easily accomplished with which type of multivibrator circuit?
a. astable
b. monostable
c. multistable
d. bistable

19.The internal circuitry of the 555 timer consists of ________, an R-S flip-flop, a transistor switch, an output buffer amplifier, and a voltage divider.
a. a comparator
b. a voltage amplifier
c. two comparators
d. a peak detector

20.With most monostable multivibrators, what is the Q output when no input trigger has occurred?
a. LOW
b. +5 V
c. SET
d. HIGH

21.an astable multivibrator requires:
a. balanced time constants
b. a pair of matched transistors
c. no input signal
d. dual J-K flip-flops

22.a crystal demonstrates the ________ effect when a mechanical force across the crystal causes a small voltage to be generated.
a. photoelectric
b. co-pitts
c. piezoelectric
d. flywheel

#### Module 5

1. Which is not considered as a linear voltage regulator?
a) Fixed output voltage regulator
c) Switching regulator
d) Special regulator
Explanation: In linear regulator’s the impedance of active element may be continuously varied to supply a desired current to the load. But in the switching regulator, a switch is turned on and off.

2. What is the dropout voltage in a three terminal IC regulator?
a) |Vin| ≥ |Vo|+2v
b) |Vin| < |Vo|-2v
c) |V in| = |Vo|
d) |Vin| ≤ |Vo|
Explanation: The unregulated input voltage must be atleast 2V more than the regulated output voltage. For example, if Vo=5V, then Vin=7V.

3. To get a maximum output current, IC regulation are provided with
b) Heat sink
c) Peak detector
d) None of the mentioned
Explanation: The load current may vary from 0 to rated maximum output current. To maintain this condition, the IC regulator is usually provided with a heat sink; otherwise it may not provide the rated maximum output current.

4. For the given circuit, let VEB(ON)=1v, ß= 15 and IO=2mA. Calculate the load current

a) IL = 23.45A
b) IL = 46.32A
c) IL = 56.87A
d) IL = 30.75A
Explanation: The equation for load current, IL = [(ß+1)IO]-[ß×(VEB(ON)/R1)]=[(15+1)×2]–[15×(1v/12 Ω)] =32-1.25 =30.75A.

5. Which type of regulator is considered more efficient?
a) All of the mentioned
b) Special regulator
c) Fixed output regulator
d) Switching regulator
Explanation: The switching element dissipates negligible power in either on or off state. Therefore, the switching regulator is more efficient than the linear regulators.

6. State the reason for thermal shutdown of IC regulator?
a) Spikes in temperature
b) Decrease in temperature
c) Fluctuation in temperature
d) Increase in temperature
Explanation: The IC regulator has a temperature sensor (built-in) which turn off the IC, when it becomes too hot (usually 125oC-150oC). The output current will drop and remains there until the IC has cooled significantly.

7. Find the difference between output current having a load of 100Ω and 120Ω for 7805 IC regulator. Consider the following specification: Voltage across the load = 5v; Voltage across the internal resistor= 350mv.
a) 8.4mA
b) 7mA
c) 9mA
d) 3.4mA
Explanation: Given the voltage across the internal resistor to be 350mv, which is less than 0.7v. Hence the transistor in 7805 is off.
When load = 100Ω, IL= IO= Ii= 5v/100 Ω = 50mA
When load=120Ω, IO= 5v/120 Ω = 41.6mA.
So, the difference between the output voltage = 50-41.6mA = 8.4mA.

8. The change in output voltage for the corresponding change in load current in a 7805 IC regulator is defined as
a) All of the mentioned
b) Line regulation
d) Input regulation
Explanation: Load regulation is defined as the change in output voltage for a change in load current and is also expressed in millivolts or as a percentage of output voltage.

9. An IC 7840 regulator has an output current =180mA and internal resistor =10Ω. Find the collector current in the output using the transistor specification: ß=15 and VEB(ON) =1.5v.
a) 270mA
b) 450mA
c) 100mA
d) 50mA
Explanation: The collector current from transistor, IC= ßIB
Where, IB= IO-(VEB(ON)/R1) = 180mA-(1.5v-10Ω) = 0.03A.
Therefore, IC= 15×0.03 = 0.45A = 450mA.

10. How the average temperature coefficient of output voltage expressed in fixed voltage regulator?
a) miilivolts/oC
b) miilivoltsoC
c) None of the mentioned
d) oC/ miilivolts
Explanation: The temperature stability or average temperature coefficient of output voltage, is the change in the output voltage per unit change in temperature and expressed in miilivolts/oC.

11. In the circuit given below, let VEB(ON)=0.8v and ß=16. Calculate the output current coming from 7805 IC and collector current coming from transistor Q1 for a load of 5Ω.

a) IO =111mA, IC= 808mA
b) IO =111mA, IC= 829mA
c) IO =111mA, IC= 881mA
d) IO =111mA, IC= 889mA
Explanation: When load = 5Ω, IL= 5v/5Ω =1A. The voltage across R1 is 7Ω × 1A=7v. Since, IL is more than 100mA, the transistor Q1 turns on and supplies the extra current required.
Therefore, IL =(ß+1)IO-[ß×(VEB(ON)/R1)
IO = [IL/(ß+1)]+ [ß×(VEB(ON)/R1) = [1/(16+1)]+[16×(0.8/2Ω)] ≅111mA.
=> IC=IL-IO=1A-111mA =889mA.

12. Calculate the output voltage for LM314 regulator. The current IADJ is very small in the order of 100µA. (Assume VREF=1.25v)

a) 17.17v
b) 34.25v
c) 89.34v
d) 23.12v
Explanation: The output voltage, VO =VREF[1=(R2/R1)]+(IADJ×R2)=1.25Vin× [1+(3kΩ/240Ω)] +( 100µA×3kΩ )= 16.875 +0.3.
=> VO=17.17v.

13. Compute the input voltage of 7805c voltage regulator with a current source that will deliver a 0.725A current to 65Ω, 10w load. (Assume reference voltage =5v)
a) Vin = 84v
b) Vin = 34v
c) Vin = 54v
d) Vin = 64v
Explanation: VO=VREF+VL =VREF+(IL×RL) = 5v+(0.725A×65Ω) = 52.125v
=> Input voltage, Vin = VO + dropout voltage = 52.125v+2v.
=> Vin ≅54v.

14. Which of the following is not a characteristic of adjustable voltage regulators?
a) Non-versatile
b) Better performance
c) Increased reliability
d) None of the mentioned

15. Biasing is done in class A mode to
a. Save power
b Improve stability
c Reduce number of sources
d. Both b and c

16. The critical inductance in mains power supply ensures that the current through ‘L’ never becomes zero. For this, critical value of inductance is
a. RL/310
b RL/450
c RL/620
d. RL/942

17. A tree in a network has a
a. Closed path
b No closed path
c No nodes
d. No branches

18. Which is a three-terminal negative voltage regulator IC
a. 78 XX
b IC 723
c LM 317
d. 79 XX

19. An antenna, when radiating, has a highly directional radiation pattern. When the antenna is receiving, its radiation pattern
a. Is more directive
b is less directive
c is same that of transmitting antenna
d. Exhibits no directivity at all.

19. In optical fiber communications
I. Inter modal dispersion can be avoided by using SMF.
II. Inter modal dispersion can be avoided by using MMF.
III. Third transmission window wavelength is used to avoid Rayleigh scattering losses.
IV. 800-900 nm window is used to avoid Rayleigh’s scattering losses.
Codes:
a. Options II and III are correct.
b Options II and IV are correct.
c Options I and III are correct.
d. Options IV and I are correct.

20. The modulation index of an AM wave in changed from 0 to 1. The transmitted power is
a. Unchanged
b Halved
c Doubled
d. Increased by 50 percent

21. Indicate the false statement. The square of the thermal noise voltage generated by a resistor is proportional to
a. Its temperature
b Its resistance
c Boltzmann constant
d. The bandwidth over which it is measured

22. The output of a dc motor depends mainly on
a. Speed and torque
b Speed and back emf
c Speed and applied voltage

23. Which one of the following is an adjustable IC voltage regulator?
a. IC 7824
b IC 7912
c LM 338
d. IC 7808

#### Module 6

1. Free running multivibrator is also called as
a) Stable multivibrator
b) Voltage control oscillator
c) Square wave oscillator
d) Pulse stretcher
Explanation: Free running multivibrator operates at a frequency which is determined by an external tuning capacitor and a resistor. On applying a dc control voltage the frequency can be shifted on either sides. This frequency deviation is directly proportional to the dc control voltage and hence it is called as ‘voltage controlled oscillator’.

2. The output voltage of phase detector is
a) Phase voltage
b) Free running voltage
c) Error voltage
d) None of the mentioned
Explanation: The phase detector compares the input frequency with the feedback frequency and produces output dc voltage called as error voltage.

3. At which state the phase-locked loop tracks any change in input frequency?
a) Free running state
b) Capture state
c) Phase locked state
d) All of the mentioned
Explanation: In the phase-locked, the output frequency is exactly same as the input signal frequency. So the circuit tracks any change in the input frequency through its repetitive action.

4. What is the function of low pass filter in phase-locked loop?
a) Improves low frequency noise
b) Removes high frequency noise
c) Tracks the voltage changes
d) Changes the input frequency
Explanation: The output voltage of a phase detector is a dc voltage and is often referred to as error voltage. This output is applied to the low pass filter which removes the high frequency noise and produces a dc level.

5. What is the need to generate corrective control voltage?
a) To maintain the lock
b) To track the frequency change
c) To shift the VCO frequency
d) All of the mentioned
Explanation: The output frequency(fo) of VCO is identical to input frequency(fs) except for a finite phase difference(φ), which generates a corrective control voltage to shift VCO frequency from fo to fs, thereby maintains the lock once locked and PLL tracks the frequency changes of the input signal.

6. At what range the PLL can maintain the lock in the circuit?
a) Lock in range
b) Input range
c) Feedback loop range
d) None of the mentioned
Explanation: The change in frequency of the incoming signal can be tracked when the PLL is locked. So, the range of frequencies over which PLL maintains the lock with the incoming signal is called as the lock in range.

7. The pull-in time depends on
a) Initial phase and frequency difference between two sign
b) Overall loop gain
c) Loop filter characteristics
d) All of the mentioned
Explanation: The pull-in time depends on the above mentioned characteristics to establish lock in the PLL circuit.

8. What is the conversion ratio of the phase detector in 565 PLL?
a) 0.14
b) 0.35
c) 0.4458
d) 0.7
Explanation: The conversion ratio of the phase detector of 565 PLL (Monolithic PLL) Kφ = 1.4/π = 0.4458.

9. Given fo = 1.2kHz and V = 13v, find the lock-in range of monolithic Phase-Locked Loop.
a) ±575Hz
b) ±720Hz
c) ±150Hz
d) ±1kHz
Explanation: The lock-in range of monolithic PLL, △fL = ±(7.8×fo)/V = ±(7.8×1.2kHz)/13 = ±720Hz.

10. Find out the incorrect statement.
Monolithic phase detector is preferred for critical applications as it is:
1. Independent of variation in amplitude
2. Independent of variation in duty cycle of the input waveform
3. Independent of variation in response time
a) 1 & 2
b) 1 & 3
c) 2 & 3
d) 1, 2 & 3
Explanation: Monolithic phase detectors are not sensitive to harmonics of the input signal and change in duty cycle of input and output frequency.

11. Determine the capture range of IC PLL 565 for a lock-in range of ± 1kHz.

a) △fc = ±31.453Hz
b) △fc = ±66.505Hz
c) △fc = ±87.653Hz
d) None of the mentioned
Explanation: The capture range is △fc = ±[△fL/ (2π×3.6×103×C]0.5 = ±[1kHz/(2π×3.6×kΩ×10µF)]0.5 = ±[1kHz/226.08×-6]0.5 = [4423]0.5 = ±66.505Hz.

12. Find the lock-in range of monolithic Phase-Locked Loop from the given diagram.

a) -fo-△fL to fo-△fL
b) -fo-△fL to -fo-△fC
c) fo-△fL to fo-△fC
d) -fo-△fC to fo-△fC
Explanation: Lock-in range of monolithic PLL is from -fo-△fL to fo-△fL.

13. At what range the PLL can maintain the lock in the circuit?
a) Lock in range
b) Input range
c) Feedback loop range
d) None of the mentioned
Explanation: The change in frequency of the incoming signal can be tracked when the PLL is locked. So, the range of frequencies over which PLL maintains the lock with the incoming signal is called as the lock in range.

14. At which state the phase-locked loop tracks any change in input frequency?
a) Free running state
b) Capture state
c) Phase locked state
d) All of the mentioned
Explanation: In the phase-locked, the output frequency is exactly same as the input signal frequency. So the circuit tracks any change in the input frequency through its repetitive action.

15. In AM detector using PLL, the phase detector is basically a multiplier which produces ________components of frequencies at its output.
a. Sum
b. Difference
c. Both a and b
d. None of the above
Answer : Both a and b

16. For a PLL IC 565 with timing resistor & timing capacitor of about 15 kΩ & 0.02μF respectively, what would be the value of output frequency (f0)?
a. 433.33 Hz
b. 833.33 Hz
c. 1000 Hz
d. 2500 Hz

17. In VCO IC 566, the value of charging & discharging is dependent on the voltage applied at ______.
a. Triangular wave output
b. Square wave output
c. Modulating input
d. All of the above

18. According to transfer characteristics of PLL, the phase error between VCO output & incoming signal must be maintained between _______ in order to maintain a lock.
a. 0 & π
b. 0 & π/2
c. 0 & 2π
d. π & 2π

19. Which characteristic of PLL is defined as the range of frequencies over which PLL can acquire lock with the input signal?
a. Free-running state
b. Pull-in time
c. Lock-in range
d. Capture range

20. In PLL, the capture range is always _________the lock range.
a. Greater than
b. Equal to
c. Less than
d. None of the above

21. Once the phase is locked, the PLL tracks the variation in the input frequency. This indicates that _____
a. Output frequency changes by same amount as that of input frequency
b. Output frequency does not change as that of input frequency
c. There is no relation between input & output frequencies
d. None of the above
Answer : Output frequency changes by same amount as that of input frequency

22. In the locked state of PLL, the phase error between the input & output is _________.
a. Maximum
b. Moderate
c. Minimum
d. All of the above

23. In communication circuits, PLL is currently applicable for __________
a. Demodulation applications
b. Tracking a carrier or synchronizing signal
c. Both a and b
d. None of the above
Answer : Both a and b

24. Basically, PLL is used to lock _______
a. Its output frequency
b. Phase to the frequency
c. Phase of the input signal
d. All of the above
Answer : All of the above