## [MCQ’s]Microcontroller and Embedded Programming

#### module 01

1. Which of the following allows the reuse of the software and the hardware components?
a) platform based design
b) memory design
c) peripheral design
d) input design
Explanation: The platform design allows the reuse of the software and the hardware components in order to cope with the increasing complexity in the design of embedded systems.

2. Which of the following is the design in which both the hardware and software are considered during the design?
a) platform based design
b) memory based design
c) software/hardware codesign
d) peripheral design
Explanation: The software/hardware codesign is the one which having both hardware and software design concerns. This will help in the right combination of the hardware and the software for the efficient product.

3. What does API stand for?
b) application programming interface
c) accessing peripheral through interface
Explanation: The platform-based design helps in the reuse of both the hardware and the software components. The application programming interface helps in extending the platform towards software applications.

4. Which activity is concerned with identifying the task at the final embedded systems?
a) high-level transformation
b) compilation
c) scheduling
Explanation: There are many design activities associated with the platforms in the embedded system and one such is the task-level concurrency management which helps in identifying the task that needed to be present in the final embedded systems.

5. In which design activity, the loops are interchangeable?
a) compilation
b) scheduling
c) high-level transformation
d) hardware/software partitioning
Explanation: The high-level transformation is responsible for the high optimizing transformations, that is, the loops can be interchanged so that the accesses to array components become more local.

6. Which design activity helps in the transformation of the floating point arithmetic to fixed point arithmetic?
a) high-level transformation
b) scheduling
c) compilation
Explanation: The high-level transformation are responsible for the high optimizing transformations, that is, for the loop interchanging and the transformation of the floating point arithmetic to the fixed point arithmetic can be done by the high-level transformation.

7. Which design activity is in charge of mapping operations to hardware?
a) scheduling
b) high-level transformation
c) hardware/software partitioning
d) compilation
Explanation: The hardware/software partitioning is the activity which is in charge of mapping operations to the software or to the hardware.

8. Which of the following is approximated during hardware/software partitioning, during task-level concurrency management?
a) scheduling
b) compilation
d) high-level transformation
Explanation: The scheduling is performed in several contexts. It should be approximated with the other design activities like the compilation, hardware/software partitioning, and task-level concurrency management. The scheduling should be precise for the final code.

9. Which of the following is a process of analyzing the set of possible designs?
a) design space exploration
b) scheduling
c) compilation
d) hardware/software partitioning
Explanation: The design space exploration is the process of analyzing the set of designs and the design which meet the specification is selected.

10. Which of the following is a meet-in-the-middle approach?
a) peripheral based design
b) platform based design
c) memory based design
d) processor design
Explanation: The platform is an abstraction layer which covers many possible refinements to a lower level and is mainly follows a meet-in-the-middle approach.

11. Which one of the following offers CPUs as integrated memory or peripheral interfaces?
a) Microcontroller
b) Microprocessor
c) Embedded system
d) Memory system
Explanation: Microcontrollers are the CPUs which have integrated memory and peripherals but microprocessor possesses external chips for memory.

12. Which of the following offers external chips for memory and peripheral interface circuits?
a) Microcontroller
b) Microprocessor
c) Peripheral system
d) Embedded system
Explanation: Microcontrollers are the CPUs which have integrated memory and peripherals whereas microprocessor offers external chips for memory.

13. How many bits does an MC6800 family have?
a) 16
b) 32
c) 4
d) 8
Explanation: MC6800 is an 8-bit processor proposed by Motorola.

14. Which of the following is a 4-bit architecture?
a) MC6800
b) 8086
c) 80386
d) National COP series
Explanation: National COP series is a 4-bit processor whereas MC6800 is an 8-bit processor, 8086 is a 16-bit processor and 80386 is a 32-bit processor.

15. What is CISC?
a) Computing instruction set complex
b) Complex instruction set computing
c) Complimentary instruction set computing
d) Complex instruction set complementary
Explanation: It is complementary to RISC architecture and has complex instruction set compared to RISC architecture.

16. How is the protection and security for an embedded system made?
a) OTP
b) IPR
c) Memory disk security
d) Security chips
Explanation: Intellectual property right provides security and protection to embedded systems.

17. Which of the following possesses a CISC architecture?
a) MC68020
b) ARC
c) Atmel AVR
d) Blackfin
Explanation: MC68020 is having a CISC architecture. CISC architecture is used for code efficiency whereas RISC architecture is used for speeding up the processor. ARC, Atmel AVR, and Blackfin are RISC architectures.

18. Which of the following is a RISC architecture?
a) 80286
b) MIPS
c) Zilog Z80
d) 80386
Explanation: MIPS possess a RISC architecture whereas 80386, 80286 and Zilog Z80 are CISC architectures.

19. Which one of the following is board based system?
a) Data bus
c) VMEbus
d) DMA bus
Explanation: VMEbus is Versa Module Europa Bus which is used as a board based system for easy manipulation. VMEbus is a computer bus standard developed for the Motorola MC6800 family and is mainly based on Eurocard sizes.

20. VME bus stands for
a) Versa module Europa bus
b) Versa module embedded bus
c) Vertical module embedded bus
d) Vertical module Europa bus
Explanation: A computer bus standard in Eurocard sizes mainly developed for Motorola MC6800 family and later on used in many applications and approved by IEEE.

21. The CISC stands for ___________
a) Computer Instruction Set Compliment
b) Complete Instruction Set Compliment
c) Computer Indexed Set Components
d) Complex Instruction set computer
Explanation: CISC is a computer architecture where in the processor performs more complex operations in one step.

22. The computer architecture aimed at reducing the time of execution of instructions is ________
a) CISC
b) RISC
c) ISA
d) ANNA
Explanation: The RISC stands for Reduced Instruction Set Computer.

23. The Sun micro systems processors usually follow _____ architecture.
a) CISC
b) ISA
c) ULTRA SPARC
d) RISC
Explanation: The Risc machine aims at reducing the instruction set of the computer.

24. The RISC processor has a more complicated design than CISC.
a) True
b) False
Explanation: The RISC processor design is more simpler than CISC and it consists of fewer transistors.

25. The iconic feature of the RISC machine among the following is _______
a) Reduced number of addressing modes
b) Increased memory size
c) Having a branch delay slot
d) All of the mentioned
Explanation: A branch delay slot is an instruction space immediately following a jump or branch.

26. Both the CISC and RISC architectures have been developed to reduce the ______
a) Cost
b) Time delay
c) Semantic gap
d) All of the mentioned
Explanation: The semantic gap is the gap between the high level language and the low level language.

27. Out of the following which is not a CISC machine.
a) IBM 370/168
b) VAX 11/780
c) Intel 80486
d) Motorola A567
Explanation: None.

28. Pipe-lining is a unique feature of _______
a) RISC
b) CISC
c) ISA
d) IANA
Explanation: The RISC machine architecture was the first to implement pipe-lining.

29. In CISC architecture most of the complex instructions are stored in _____
a) Register
b) Diodes
c) CMOS
d) Transistors
Explanation: In CISC architecture more emphasis is given on the instruction set and the instructions take over a cycle to complete.

30. Which of the architecture is power efficient?
a) CISC
b) RISC
c) ISA
d) IANA
Explanation: Hence the RISC architecture is followed in the design of mobile devices.

31. Which are the processors based on RISC?
a) SPARC
b) 80386
c) MC68030
d) MC68020
Explanation: SPARC and MIPS processors are the first generation processors of RISC architecture.

32. What is 80/20 rule?
a) 80% instruction is generated and 20% instruction is executed
b) 80% instruction is executed and 20% instruction is generated
c) 80%instruction is executed and 20% instruction is not executed
d) 80% instruction is generated and 20% instructions are not generated
Explanation: 80% of instructions are generated and only 20% of the instruction set is executed that is, by simplifying the instructions, the performance of the processor can be increased which lead to the formation of RISC that is reduced instruction set computing.

33. Which of the architecture is more complex?
a) SPARC
b) MC68030
c) MC68030
d) 8086
Explanation: SPARC have RISC architecture which has a simple instruction set but MC68020, MC68030, 8086 have CISC architecture which is more complex than CISC.

34. Which is the first company who defined RISC architecture?
a) Intel
b) IBM
c) Motorola
d) MIPS
Explanation: In 1970s IBM identified RISC architecture.

35. Which of the following processors execute its instruction in a single cycle?
a) 8086
b) 8088
c) 8087
d) MIPS R2000
Explanation: MIPS R2000 possess RISC architecture in which the processor executes its instruction in a single clock cycle and also synthesize complex operations from the same reduced instruction set.

36. How is memory accessed in RISC architecture?
b) opcode instruction
c) memory instruction
d) bus instruction
Explanation: The data of memory address is loaded into a register and manipulated, its contents are written out to the main memory.

37. Which of the following has a Harvard architecture?
a) EDSAC
b) SSEM
c) PIC
d) CSIRAC
Explanation: PIC follows Harvard architecture in which the external bus architecture consist of separate buses for instruction and data whereas SSEM, EDSAC, CSIRAC are stored program architecture.

38. Which of the following statements are true for von Neumann architecture?
a) shared bus between the program memory and data memory
b) separate bus between the program memory and data memory
c) external bus for program memory and data memory
d) external bus for data memory only
Explanation: von Neumann architecture shares bus between program memory and data memory whereas Harvard architecture have a separate bus for program memory and data memory.

39. What is CAM stands for?
Explanation: Non-von Neumann architecture is based on content-addressable memory.

40. Which of the following processors uses Harvard architecture?
a) TEXAS TMS320
b) 80386
c) 80286
d) 8086
Explanation: It is a digital signal processor which have small and highly optimized audio or video processing signals. It possesses multiple parallel data bus.

41. Which company further developed the study of RISC architecture?
a) Intel
b) Motorola
c) university of Berkeley
d) MIPS
Explanation: The University of Berkeley and Stanford university provides the basic architecture model of RISC.

42. Princeton architecture is also known as
a) von Neumann architecture
b) Harvard
c) RISC
d) CISC
Explanation: The von Neumann architecture is also known as von Neumann model or Princeton architecture.

43. Who coined the term RISC?
a) David Patterson
b) von Neumann
c) Michael J Flynn
d) Harvard
Explanation: David Patterson of Berkeley university coined the term RISC whereas Michael J Flynn who first views RISC.

44. Which of the following is an 8-bit RISC Harvard architecture?
a) AVR
b) Zilog80
c) 8051
d) Motorola 6800
Explanation: AVR is an 8-bit RISC architecture developed by Atmel. Zilog80, 8051, Motorola 6800 are having CISC architectures.

45. Which of the following processors has CISC architecture?
a) AVR
b) Atmel
c) Blackfin
d) Zilog Z80
Explanation: Zilog80 have CISC architecture whereas AVR, Atmel and blackfin possess RISC architecture.

47. Any digital computer can be used for DSP.
a) True
b) False
Explanation: DSP is the use of a fast digital computer or digital circuitry to perform processing on digital signals. Any digital computer with sufficient speed and memory can be used for DSP.

48. What happens after the signal is passed through the analog to digital converter in a DSP?
a) Changed back to analog
b) Stored in a RAM
c) Amplified
d) Attenuated
Explanation: When the signal is converted from analog to digital it is a sequence of binary numbers which is stored in the RAM. A user defined code that is usually stored in the ROM performs mathematical and other manipulations after which it is converted back into analog signals.

49. Who is credited with creating the stored program concept?
a) John Von Neumann
b) Larry Page
c) Alan Turing
d) Ken Thompson
Explanation: Physicist John Von Neumann is generally credited with creating the stored program concept that is the basis of operation of all digital computers. Binary words representing computer instructions are stored sequentially in a memory to form a program. The instructions are fetched and executed one at a time at high speed.

50. What is the accessibility limitation of only one data or instruction set at a time from the memory called?
a) Von Neumann limitation
b) Von Neumann limit
c) Von Neumann speed
d) Von Neumann bottleneck
Explanation: The accessibility limitation of only one data or instruction set at a time from the memory is called as Von Neumann bottleneck. This has the effect of greatly limiting the execution speed.

51. Which type of architecture uses different storage space for program code and the data?
a) Von Neumann architecture
b) Harvard architecture
c) Fragmented architecture
d) Split cell architecture
Explanation: In a Harvard architecture microprocessor, there are two memories, a program or instruction memory, usually a ROM, and a data memory, which is a RAM. Also, there are two data paths into and out of the CPU between the memories. Because both instructions and data can be accessed simultaneously, very high-speed operation is possible.

52. What is the reason for the need of high speed DSP?
a) Less power consumption at higher speeds
b) Better processing capabilities
c) High sampling frequency
d) Easily programmable
Explanation: The time taken for input/output and the processing time together must be smaller than the sampling period to ensure the continuous flow of data. Since high sampling frequencies are needed for accurately converting the analog signal to digital, high speed DSP is a must.

53. Selectivity in a DSP is better than its analog equivalent.
a) True
b) False
Explanation: With DSP, the filters can have characteristics far superior to those of equivalent analog filters. Selectivity can be better because of the ease of controlling binary numbers, and the passband or reject band can be customized to the application.

54. Reduction in the number of binary words required to represent an analog signal is called ________
a) Undersampling
b) Oversampling
c) Data compression
d) Data minimization
Explanation: Data compression is a process that reduces the number of binary words needed to represent a given analog signal. Since analog to digital conversion produces a huge amount of data, for transmission it is a necessity that data is compressed.

55. What is the process of examining the frequency content of a signal?
a) Signal decoding
b) Spectrum analysis
c) Signal analysis
d) Data analysis
Explanation: Spectrum analysis is the process of examining a signal to determine its frequency content. Algorithms such as discrete Fourier transform (DFT) and FPGA is used to analyze the frequency content of an input signal.

56. What is the program that is used to speed the spectrum analysis process?
a) DDFT
b) FDFT
c) FGPA
d) Fast Fourier transforms
Explanation: The DFT is a complex program that is long and time-consuming to run. In general, computers are not fast enough to perform DFT in real time as the signal occurs. Therefore, a special version of the algorithm has been developed to speed up the calculation. Known as the fast Fourier transform (FFT), it permits real-time signal spectrum analysis.

57. Which of the following is not possible when the signal is analog?
a) Phase shifting
b) Equalization
c) Modulation
d) Data compression
Explanation: Data compression is done by checking redundancy in data. Data redundancy checking is only possible when the data is in digital form and hence data compression cannot be done in analog signals.

58. In the frequency sampling method for FIR filter design, we specify the desired frequency response Hd(ω) at a set of equally spaced frequencies.
a) True
b) False
Explanation: In the frequency sampling method, we specify the frequency response Hd(ω) at a set of equally spaced frequencies, namely ωk=2πM(k+α)

59. To reduce side lobes, in which region of the filter the frequency specifications have to be optimized?
a) Stop band
b) Pass band
c) Transition band
d) None of the mentioned
Explanation: To reduce the side lobes, it is desirable to optimize the frequency specification in the transition band of the filter. This optimization can be accomplished numerically on a digital computer by means of linear programming techniques.

60. What is the frequency response of a system with input h(n) and window length of M?
a) M1n=0h(n)ejωn
b) Mn=0h(n)ejωn
c) Mn=0h(n)ejωn
d) M1n=0h(n)ejωn
Explanation: The desired output of an FIR filter with an input h(n) and using a window of length M is given as
H(ω)=M1n=0h(n)ejωn

61. What is the relation between H(k+α) and h(n)?
a) H(k+α)=M+1n=0h(n)ej2π(k+α)n/M; k=0,1,2…M+1
b) H(k+α)=M1n=0h(n)ej2π(k+α)n/M; k=0,1,2…M-1
c) H(k+α)=Mn=0h(n)ej2π(k+α)n/M; k=0,1,2…M
d) None of the mentioned
Explanation: We know that
ωk=2πM(k+α) and H(ω)=M1n=0h(n)ejωn
Thus from substituting the first in the second equation, we get
H(k+α)=M1n=0h(n)ej2π(k+α)n/M; k=0,1,2…M-1

62. Which of the following is the correct expression for h(n) in terms of H(k+α)?
a) 1MM1k=0H(k+α)ej2π(k+α)n/M; n=0,1,2…M-1
b) M1k=0H(k+α)ej2π(k+α)n/M; n=0,1,2…M-1
c) 1MM+1k=0H(k+α)ej2π(k+α)n/M; n=0,1,2…M+1
d) M+1k=0H(k+α)ej2π(k+α)n/M; n=0,1,2…M+1
Explanation: We know that
H(k+α)=M1n=0h(n)ej2π(k+α)n/M; k=0,1,2…M-1
If we multiply the above equation on both sides by the exponential exp(j2πkm/M), m=0,1,2….M-1 and sum over k=0,1,….M-1, we get the equation
h(n)=1MM1k=0H(k+α)ej2π(k+α)n/M; n=0,1,2…M-1

63. Which of the following is equal to the value of H(k+α)?
a) H*(M-k+α)
b) H*(M+k+α)
c) H*(M+k-α)
d) H*(M-k-α)
Explanation: Since {h(n)} is real, we can easily show that the frequency samples {H(k+α)} satisfy the symmetry condition
H(k+α)= H*(M-k-α).

64. The linear equations for determining {h(n)} from {H(k+α)} are not simplified.
a) True
b) False
Explanation: The symmetry condition, along with the symmetry conditions for {h(n)}, can be used to reduce the frequency specifications from M points to (M+1)/2 points for M odd and M/2 for M even. Thus the linear equations for determining {h(n)} from {H(k+α)} are considerably simplified.

65. The major advantage of designing linear phase FIR filter using frequency sampling method lies in the efficient frequency sampling structure.
a) True
b) False
Explanation: Although the frequency sampling method provides us with another means for designing linear phase FIR filters, its major advantage lies in the efficient frequency sampling structure, which is obtained when most of the frequency samples are zero.

66. Which of the following is introduced in the frequency sampling realization of the FIR filter?
a) Poles are more in number on unit circle
b) Zeros are more in number on the unit circle
c) Poles and zeros at equally spaced points on the unit circle
d) None of the mentioned
Explanation: There is a potential problem for frequency sampling realization of the FIR linear phase filter. The frequency sampling realization of the FIR filter introduces poles and zeros at equally spaced points on the unit circle.

67. In a practical implementation of the frequency sampling realization, quantization effects preclude a perfect cancellation of the poles and zeros.
a) True
b) False
Explanation: In the ideal situation, the zeros cancel the poles and, consequently, the actual zeros of the H(z) are determined by the selection of the frequency samples H(k+α). In a practical implementation of the frequency sampling realization, however, quantization effects preclude a perfect cancellation of the poles and zeros.

68. In the frequency sampling method for FIR filter design, we specify the desired frequency response Hd(ω) at a set of equally spaced frequencies.
a) True
b) False
Explanation: According to the frequency sampling method for FIR filter design, the desired frequency response is specified at a set of equally spaced frequencies.

69. What is the equation for the frequency ωk in the frequency response of an FIR filter?
a) πM(k+α)
b) 4πM(k+α)
c) 8πM(k+α)
d) 2πM(k+α)
Explanation: In the frequency sampling method for FIR filter design, we specify the desired frequency response Hd(ω) at a set of equally spaced frequencies, namely
ωk=2πM(k+α)
where k=0,1,2…M-1/2 and α=0 0r 1/2.

70. Why is it desirable to optimize frequency response in the transition band of the filter?
a) Increase side lobe
b) Reduce side lobe
c) Increase main lobe
d) None of the mentioned
Explanation: To reduce side lobes, it is desirable to optimize the frequency specification in the transition band of the filter.

#### Module 02

1. 8051 microcontrollers are manufactured by which of the following companies?
a) Atmel
b) Philips
c) Intel
d) All of the mentioned
Explanation: 8051 microcontrollers are manufactured by Intel, Atmel, Philips/Signetics, Infineon, Dallas Semi/Maxim.

2. AT89C2051 has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
Explanation: It has 128 bytes of RAM in it.

3. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
Explanation: It has two 16 bit registers DPTR and PC.

4. When 8051 wakes up then 0x00 is loaded to which register?
a) PSW
b) SP
c) PC
d) None of the mentioned
Explanation: When 8051 wakes up, Program Counter (PC) loaded with 0000H. Because of this in 8051 first opcode is stored in ROM address at 0000H.

5. When the microcontroller executes some arithmetic operations, then the flag bits of which register are affected?
a) PSW
b) SP
c) DPTR
d) PC
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow, parity, register bank select bits etc which are affected during such operations.

6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction
MOV A,#9C
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and AC are set to 1. In the result, the number of 1’s present are even so parity flag is set to zero.

7. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2 RS1=1 and RS0=0 which are fourth and third bit of the register respectively.

8. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
Explanation: If we push elements onto the stack then the stack pointer increases with every push of element.

9. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.

10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.

11. What do you mean by micro in microcontroller?
a) Distance between 2 IC’s
b) Distance between 2 transistors
c) Size of a controller
d) Distance between 2 pins
Explanation: Micro means 10-6 which gives the distance between 2 element transistors which is called as Micron Technology.

12. What is the bit size of the 8051 microcontroller?
a) 8-bit
b) 4-bit
c) 16-bit
d) 32-bit
Explanation: It is an 8-bit microcontroller which means most of the operations are limited to 8 bit only.

13. Name the architecture and the instruction set for microcontroller?
a) Van- Neumann Architecture with CISC Instruction Set
b) Harvard Architecture with CISC Instruction Set
c) Van- Neumann Architecture with RISC Instruction Set
d) Harvard Architecture with RISC Instruction Set
Explanation: Harvard architecture has different memory spaces for both program memory and data memory with Complex Instruction Set Computer(CISC). The difference between CISC and RISC is RISC has few instructions than CISC. Where as in Van- Neumann, program and data memory are same. Van- Neumann is also called as Princeton architecture.

14. Number of I/O ports in the 8051 microcontroller?
a) 3 ports
b) 4 ports
c) 5 ports
d) 4 ports with last port having 5 pins
Explanation: It has 4 ports with port0 act as I/O port and also multiplexing of address and data bus. Port1act as I/O port. Port 2 act as I/O and also like address lines. Port 3 act as I/O and also for external peripherals.

15. Is ROM is used for storing data storage?
a) True
b) False
Explanation: RAM is used for storing data storage and ROM is used for storing program memory.

16. SCON in serial port is used for which operation?
a) Transferring data
b) Receiving data
c) Controlling
d) Controlling and transferring
Explanation: There are 2 pins available in serial port. One is used for transmission and other is used for receiving data. SCON is the bit in the serial port which is used for controlling the operation.

17. Program counter stores what?
b) Address of the next instruction
c) Data of the before execution to be executed
d) Data of the execution instruction
Explanation: Points to the address of the next instruction to be executed from ROM. It is 16 bit register means the 8051 can access program address from 0000H to FFFFH. Total 64KB of code.

18. Auxiliary carry is set during which condition?
a) When carry is generated from D3 to D4
b) When carry is generated from D7
c) When carry is generated from both D3 to D4 and D7
d) When carry is generated at either D3 to D4 or D7
Explanation: When carry is generated from D3 to D4, it is set to 1, it is used in BCD arithmetic.

19. What is order of the assembly and running 8051 program?
i) Myfile.asm
ii) Myfile.lst
iii) Myfile.obj
iv) Myfile.hex
a) i,ii,iii,iv
b) ii,iii,I,iv
c) iv,ii,I,iii
d) iii,ii,I,iv
Explanation: After writing the program in editor and compilation first .asm, .lst, .obj, .hex are created.

20. The use of Address Latch Enable is to multiplex address and data memory.
a) True
b) False
Explanation: That is used for multiplexting address and data ie., the same line carries address and data. To indicate when it carries address, ALE is emitted by 8051.

21. Which pin provides a reset option in 8051?
a) Pin 1
b) Pin 8
c) Pin 11
d) Pin 9

Explanation: Reset pin is utilized to set the micro controller 8051 to its primary values, whereas the micro controller is functioning or at the early beginning of application. The reset pin has to be set elevated for two machine rotations.

22. External Access is used to permit ____________
a) Peripherals
b) Power supply
c) ALE
d) Memory interfacing
Explanation: External Access input is employed to permit or prohibit outer memory interfacing. If there is no outer memory needed, this pin is dragged by linking it to Vcc.

23. What is the address range of SFRs?
a) 80h to feh
b) 00h to ffh
c) 80h to ffh
d) 70h to 80h
Explanation: In 8051 there certain registers which uses the RAM addresses from80h to ffh. These are called as Special Function Registers. Some of the SRFrs are I/o ports and control operations as TCON, SCON, PCON.

24. How many interrupts are there in micro controller?
a) 3
b) 6
c) 4
d) 5
Explanation: An interrupt is an external or internal event that disturbs the microcontroller to inform if that needs its services. There are 5 interrupts :
Timer 0 overflow interrupt
Timer 1 overflow interrupt
External Interrupt 0
External Interrupt 1
Serial port events.

25. Timer 0 is a ________ bit register.
a) 32-bit
b) 8-bit
c) 16-bit
d) 10-bit
Explanation: The Timer 0 is a 16-bit register and can be treated as two 8-bit registers and these can be accessed similarly to any other registers.

26. Which of the following is not one of the SFR addresses of the ports of 8051?
a) 80H
b) 90H
c) A0H
d) NONE
Explanation: The SFR addresses of the ports P0, P1, P2 and P3 are 80H, 90H, A0H and B0H respectively.

27. Each port line of a port can individually source a current of upto
a) 0.2 mA
b) 0.25 mA
c) 0.5 mA
d) 0.75 mA
Explanation: Each port line of a port can individually source a current of upto 0.5 mA.

28. Each port line of a port can individually sink a current of upto
a) 2 mA
b) 8 mA
c) 5 mA
d) 1 mA
Explanation: Each port line of a port can individually sink a current of upto 8 mA.

29. The number of TTL inputs that can be sinked by the port 0 when a logic 0 is sent to a port line as an output port is
a) 2
b) 4
c) 6
d) 8
Explanation: When a logic 0 is sent to a port line as an output port, it can sink 8 LS TTL inputs. Port 0 is used as data bus during external interfacing whenever required.

30. The open drain bidirectional (input or output) port with internal pullups is
a) Port 0
b) Port 1
c) Port 2
d) Port 3
Explanation: Port 0 is an open drain bidirectional (input or output) port with internal pullups. Port 1, Port 2, Port 3 are 8-bit bidirectional ports.

31. The port that can source or sink 4 LS TTL inputs when being used as an output port on each of its line is
a) Port 1
b) Port 2
c) Port 3
d) all of the mentioned
Explanation: The ports P1, P2 and P3 can source or sink 4 LS TTL inputs when being used as an output port on each of its line.

32. The port that will source a current of 500 micro amperes when being used as input ports is
a) 0.5 mA
b) 0.25 mA
c) 250 micro amperes
d) 500 micro amperes
Explanation: Port 3 pins which are externally pulled low when being used as input pins will source current of 500 micro amperes.

33. If the EA(active low) signal is grounded then the execution
a) directly start from main memory
b) directly start from 16 bit address in main memory
c) directly start from 16 bit address in program memory
d) directly start from RAM
Explanation: For interfacing external program memory, EA(active low) pin must be grounded. If the EA(active low) signal is grounded then the execution will start directly from the 16-bit address 0000H in external program memory.

34. When the port lines of a port are to be used as input lines then the value that must be written to the port address is
a) F0H
b) 0FH
c) FFH
d) 00H
Explanation: When the port lines of a port are to be used as input lines then ‘FF’H must be written to the port address.

35. Port 1 lines are used during programming of
a) external EPROM and EEPROM
b) external ROM and RAM
c) internal ROM and RAM
d) internal EPROM and EEPROM
Explanation: Port 1 lines are used as lower byte of 16-bit address bus during programming of internal EPROM or EEPROM.

36. The configuration in which each LED receives operating current of 8 mA from power supply while the port lines sink the current on each port line is
a) common port configuration
b) common anode configuration
c) common cathode configuration
d) none of the mentioned
Explanation: The common anode configuration is preferred to that of other configurations as in common anode configuration, each LED receives operating current of 8 mA from power supply while the port lines sink the current on each port line.

37. What is the clock source for the timers?
a) some external crystal applied to the micro-controller for executing the timer
b) from the crystal applied to the micro-controller
c) through the software
d) through programming
Explanation: Timer’s clock source is the crystal that is applied to the controller.

38. What is the frequency of the clock that is being used as the clock source for the timer?
a) some externally applied frequency f’
b) controller’s crystal frequency f
c) controller’s crystal frequency /12
d) externally applied frequency/12
Explanation: The frequency of the clock source for the timer is equal to f/12(where f is the frequency of the crystal).

39. What is the function of the TMOD register?
a) TMOD register is used to set various operation modes of timer/counter
b) TMOD register is used to load the count of the timer
c) Is the destination or the final register where the result is obtained after the operation of the timer
d) Is used to interrupt the timer
Explanation: TMOD is used to set various operation modes of timer/counter by the programmer.

40. What is the maximum delay that can be generated with the crystal frequency of 22MHz?
a) 2978.9 sec
b) 0.011 msec
c) 11.63 sec
d) 2.97 msec
Explanation: For generating the maximum delay we have to multiply the maximum number of counts with the time period required to execute one machine cycle( 65536*1/22MHz).

41. Auto reload mode is allowed in which mode of the timer?
a) Mode 0
b) Mode 1
c) Mode 2
d) Mode 3
Explanation: Auto reload is allowed in the Mode 2 of the timer because here in this mode, we don’t need to load the count again and again in the register.

42. Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2?
a) 00FFH,0FFFH,FFFFH
b) 1FFFH,0FFFH,FFFFH
c) 1FFFH,FFFFH,00FFH
d) 1FFFH,00FFH,FFFFH
Explanation: For Mode 0 13 bit value is used so 1FFFH is chosen to be the roll over value. Similarly for Mode 1 FFFFH and for Mode 2 FFH is the roll over value for the timers and counter.

43. What steps are followed when we need to turn on any timer?
a) load the count, start the timer, keep monitoring it, stop the timer
b) load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer
c) load the TMOD register, start the timer, load the count, keep monitoring it, stop the timer
d) none of the mentioned
Explanation: When any timer is to turn on, then firstly we have to load the TMOD register and the count. Then the timer is to get started. After then, we need to monitor the timer properly and then when the roll over condition arises then the timer is to be stopped.

45. If Timer 0 is to be used as a counter, then at what particular pin clock pulse need to be applied?
a) P3.3
b) P3.4
c) P3.5
d) P3.6
Explanation: If Timer 0 is to be used as a counter, then a pulse has to be applied at P3.4 and if it is for Timer 1 then the clock pulse has to be applied at the pin P3.5.

46. In the instruction “MOV TH1,#-3”, what is the value that is being loaded in the TH1 register?
a) 0xFCH
b) 0xFBH
c) 0xFDH
d) 0xFEH
Explanation: Negative value is loaded in 2’s complement form. -3 represented in 2’s complement form as FDH.
Steps to convert into 2’s complement:

3 → 0000 0011       	Binary Equivalent of ‘3’
→  1111 1100          1’s Complement of decimal ‘-3’
→  1111 1101       	2’s Complement of decimal ‘-3’
F     D           Hex Equivalent of ‘-3’

47. TF1, TR1, TF0, TR0 bits are of which register?
a) TMOD
b) SCON
c) TCON
d) SMOD
Explanation: All of these bits are part of TCON (Timer Control) register. TF0 and TF1 are used to check overflow of timer 0 and timer 1 respectively. TR0 and TR1 are timer control bits used to start and stop of timer 0 and timer 1 respectively.

48. Which devices are specifically being used for converting serial to parallel and from parallel to serial respectively?
a) timers
b) counters
c) registers
d) serial communication
Explanation: Some registers like the parallel in serial out and serial in parallel out are used to convert serial data into parallel and vice versa respectively.

49. What is the difference between UART and USART communication?
a) they are the names of the same particular thing, just the difference of A and S is there in it
b) one uses asynchronous means of communication and the other uses synchronous means of communication
c) one uses asynchronous means of communication and the other uses asynchronous and synchronous means of communication
d) one uses angular means of the communication and the other uses linear means of communication
Explanation: UART stands for Universal Asynchronous receiver-transmitter and USART stands for Universal Synchronous and Asynchronous receiver-transmitter.

50. Which of the following best describes the use of framing in asynchronous means of communication?
a) it binds the data properly
b) it tells us about the start and stops of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control
Explanation: In data framing in asynchronous means of communication, the data is packed between the start and the stop bit. This is done so as to tell the other computer about the start and the end of the data.

51. Which of the following signal control the flow of data?
a) RTS
b) DTR
c) RTS & DTR
d) None of the mentioned
Explanation: RTS is a request to send control signal which is a control for the flow of data. On the other hand DTR is a Data Terminal Ready control signal which tells about the current status of the DTE.

52. Which of the following is the logic level understood by the micro-controller/micro-processor?
a) TTL logic level
b) RS232 logic level
c) None of the mentioned
d) TTL & RS232 logic level
Explanation: TTL logic or the transistor logic level is the logic that is understood by the micro-controllers/microprocessors.

53. What is a null modem connection?
a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication
Explanation: In null modem connection the RxD of one is the TxD for the other.

54. Which of the following best states the reason that why baud rate is mentioned in serial communication?
a) to know about the no of bits being transmitted per second
b) to make the two devices compatible with each other, so that the transmission becomes easy and error free
c) to use Timer 1
d) for wasting memory
Explanation: To make two devices compatible with each other baud rate is mentioned in the serial communication so that the transmission becomes easy and error free.

55. With what frequency UART operates( where f denoted the crystal frequency )?
a) f/12
b) f/32
c) f/144
d) f/384
Explanation: UART frequency is the crystal frequency f/12 divided by 32, that comes out to be f/384.

56. What is the function of the SCON register?
a) to control SBUF and SMOD registers
b) to program the start bit, stop bit, and data bits of framing
c) to control SMOD registers
d) none of the mentioned
Explanation: SCON register is mainly used for programming the start bits, stop bits and data bits of framing. As it consists of bits like RB8, TB8, SM0, SM1, SM2 etc.

57. What should be done if we want to double the baud rate?
a) change a bit of the TMOD register
b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
Explanation: PCON register consists of SMOD bit as its D7 bit, so if we set this bit then the baud rate gets doubled.

58. When an interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?
a) to the next instruction which is to be executed
b) to the first instruction of ISR
c) to a fixed location in memory called interrupt vector table
d) to the end of the program
Explanation: When an interrupt occurs, then it jumps to a fixed memory location in memory called the interrupt vector table that holds the address of the Interrupt Service Routine.

59. What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?
a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be disabled or the contents of the IE register becomes null.

60. After RETI instruction is executed then the pointer will move to which location in the program?
a) next interrupt of the interrupt vector table
b) immediate next instruction where interrupt is occurred
c) next instruction after the RETI in the memory
d) none of the mentioned
Explanation: When the RETI instruction is executed, PC will fetch 2-bytes (address) from top of stack which is stored when interrupt is occurred. This will return to the place where interrupt is occurred and starts executing instructions.

61. Which pin of the external hardware is said to exhibit INT0 interrupt?
a) pin no 10
b) pin no 11
c) pin no 12
d) pin no 13
Explanation: INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low leveled pulse.

62. Which bit of the IE register is used to enable TxD/RxD interrupt?
a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
Explanation: IE.D4 is used to enable RS interrupt or the serial communication interrupt.

63. Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assuming initially all bits of the IE register are zero)?
a) EX0=1
b) EA=1
c) any of the mentioned
d) EX0=1 & EA=1
Explanation: For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is set to enable all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and mask the other enabled interrupts.

64. Why normally LJMP instructions are the topmost lines of the ISR?
a) so as to jump to some other location where there is a wider space of memory available to write the codes
b) so as to avoid overwriting of other interrupt instructions
c) all of the mentioned
d) none of the mentioned
Explanation: There is a small space of memory present in the vector table between two different interrupts so in order to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is available.

65. Which register is used to make the interrupt level or an edge triggered pulse?
a) TCON
b) IE
c) IPR
d) SCON
Explanation: TCON register is used to make any interrupt level or edge triggered.

66. What is the disadvantage of a level triggered pulse?
a) a constant pulse is to be maintained for a greater span of time
b) another interrupt may be generated if the low-level signal is not removed before the ISR is finished
c) it is difficult to produce
d) another interrupt may be caused if the signal is still low before the completion of the last instruction
Explanation: In a level triggered interrupt, if the low signal at interrupt pin must be removed before the execution of last instruction of the ISR i.e. RETI. If low signal at interrupt pin is not removed before completing the ISR then it will be generating another interrupt.

67. What is the correct order of priority that is set after a controller gets reset?
a) RI/TI > TF1 > TF0 > INT1 > INT0
b) RI/TI < TF1 < TF0 < INT1 < INT0
c) INT0 > TF0 > INT1 > TF1 > RI/TI
d) INT0 < TF0 < INT1 < TF1 < RI/TI
Explanation: On reset Interrupt Priorities are as INT0 > TF0 > INT1 > TF1 > RI/TI, where ‘>’ is used to denote highest priority.

68. Which of the following is not an addressing mode of 8051?
a) register instructions
b) register specific instructions
d) none
Explanation: The six addressing modes of 8051 are
3. Register instructions
4. Register specific(Register Implicit) instructions
5. Immediate mode

69. The symbol, ‘addr 16’ represents the 16-bit address which is used by the instructions to specify the
c) destination address of call or jump
d) source address of call or jump
Explanation: The symbol, ‘addr 16’ represents the 16-bit destination address which is used by the LCALL or LJMP instruction to specify the call or jump destination address, within 64 Kbytes program memory.

70. The storage of addresses that can be directly accessed is
a) external data RAM
b) internal data ROM
c) internal data RAM and SFRS
d) external data ROM and SFRS
Explanation: Only internal data RAM and SFRS can be directly addressed in direct addressing mode.

71. The address register for storing the 16-bit addresses can only be
a) stack pointer
b) data pointer
c) instruction register
d) accumulator
Explanation: The address register for storing the 16-bit addresses can only be data pointer.

a) R0 of the selected bank of register
b) R1 of the selected bank of register
c) Stack pointer
d) All of the mentioned
Explanation: The registers R0 and R1 of the selected bank of registers or stack pointer can be used as address registers for storing the 8-bit addresses.

73. The instruction, ADD A, R7 is an example of
a) register instructions
b) register specific instructions
d) none
Explanation: In register instructions addressing mode, operands are stored in the registers R0-R7 of the selected register bank. One of these registers is specified in the instruction.

74. The addressing mode, in which the instructions has no source and destination operands is
a) register instructions
b) register specific instructions
Explanation: In register specific instructions addressing mode, the instructions don’t have source and destination operands. Some of the instructions always operate only on a specific register.

75. The instruction, RLA performs
a) rotation of address register to left
b) rotation of accumulator to left
c) rotation of address register to right
d) rotation of accumulator to right
Explanation: The instruction, RLA rotates accumulator left.

76. The instruction, ADD A, #100 performs
b) 100(decimal) is subtracted from the accumulator
c) 100(decimal) is added to contents of an accumulator
d) none
Explanation: Immediate data 100(decimal) is added to the contents of the accumulator.

77. In which of these addressing modes, a constant is specified in the instruction, after the opcode byte?
a) register instructions
b) register specific instructions
d) immediate mode
Explanation: In immediate mode, an immediate data, i.e. a constant is specified in the instruction, after the opcode byte.

78. The only memory which can be accessed using indexed addressing mode is
a) RAM
b) ROM
c) Main memory
d) Program memory
Explanation: Only program memory can be accessed using the indexed addressing mode.

79. The data address of look-up table is found by adding the contents of
a) accumulator with that of program counter
b) accumulator with that of program counter or data pointer
c) data register with that of program counter or accumulator
d) data register with that of program counter or data pointer
Explanation: The look-up table data address is found out by adding the contents of register accumulator with that of the program counter or data pointer.

80. The assembler directives which are the hints using some predefined alphabetical strings are given to
a) processor
b) memory
c) assembler
d) processor & assembler
Explanation: These directives help the assembler to correctly understand the assembly language programs to prepare the codes.

81. The directive used to inform the assembler, the names of the logical segments to be assumed for different segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d) DB
Explanation: In ALP, each segment is given a name by using the directive ASSUME
SYNTAX: ASSUME segment:segment_name
Eg: ASSUME CS:Code
here CS is the Code segment and code is the name assumed to the segment.

82. Match the following

   a) DB          1) used to direct the assembler to reserve only 10-bytes
b) DT          2) used to direct the assembler to reserve only 4 words
c) DW          3) used to direct the assembler to reserve byte or bytes
d) DQ          4) used to direct the assembler to reserve words

a) a-3, b-2, c-4, d-1
b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2
Explanation: These directives are used for allocating memory locations in the available memory.

83. The directive that marks the end of an assembly language program is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
Explanation: The directive END is used to denote the completion of the program.

84. The directive that marks the end of a logical segment is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
Explanation: The directive ENDS is used to end a segment where as the directive END is used to end the program.

85. The directive that updates the location counter to the next even address while executing a series of instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU
Explanation: The directive updates location counter to next even address if the current location counter contents are not even.

86. The directive that directs the assembler to start the memory allotment for a particular segment/block/code from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP
Explanation: If an ORG is written then the assembler initiates the location counter to keep the track of allotted address for the module as mentioned in the directive.
If the directive is not present, then the location counter is initialized to 0000H.

87. The directive that marks the starting of the logical segment is
a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC
Explanation: The directive SEGMENT indicates the beginning of the segment.

88. The recurrence of the numerical values or constants in a program code is reduced by
a) ASSUME
b) LOCAL
c) LABEL
d) EQU
Explanation: In this, the recurring/repeating value is assigned with a label. The label is placed instead of the numerical value in the entire program code.

89. The labels or constants that can be used by any module in the program is possible when they are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used by any module in the program.

90. When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory

91. DAA command adds 6 to the nibble if:
a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.

92. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of the register or some immediate value. So A-R4 is being executed.

93. A valid division instruction always makes:
a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
Explanation: When we divide two numbers then AC and CY become zero.

94. In 8 bit signed number operations, OV flag is set to 1 if:
a) a carry is generated from D7 bit
b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to 1.

95. In unsigned number addition, the status of which bit is important?
a) OV
b) CY
c) AC
d) PSW
Explanation: If unsigned numbers operations are involved, then the status of CY flag is important and in signed number operation the status of OV flag is important.

96. Which instructions have no effect on the flags of PSW?
a) ANL
b) ORL
c) XRL
d) All of the mentioned
Explanation: These instructions are the arithmetic operations and the flags are affected by the data copy instructions, so all these instructions don’t affect the bits of the flag.

97. ANL instruction is used _______
a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to mask the status of the bits of the register.

98. CJNE instruction makes _______
a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
d) none of the mentioned
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not equal and it resets CY if the destination address is larger then the source address and sets CY if the destination address is smaller then the source address.

99. XRL, ORL, ANL commands have _______
a) accumulator as the destination address and any register, memory or any immediate data as the source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the source address
d) any register as the destination address and any immediate data as the source address
Explanation: These commands have accumulator as the destination address and any register, memory or any immediate data as the source address.

#### Module 03

1. Why two pins for ground are available in ADC0804?
b) for controlling the analog and the digital pins of the controller
c) for both parts of the chip respectively
d) for isolate analog and digital signal
Explanation: Two grounds are available in ADC0804 to isolate analog signal from digital signal. This isolation provides accuracy in digital output.

2. What is the function of the WR pin?
a) its active high input used to inform ADC0804 to the end of conversion
b) its active low input used to inform ADC0804 to the end of conversion
c) its active low input used to inform ADC0804 to the start of conversion
d) its active high input used to inform ADC0804 to the start of conversion
Explanation: WR is active low input used to inform the ADC0804 to start the conversion process.

3. State which of the following statements are false?
a) CLK IN pin used for External Clock Input or Internal Clock with external RC element
b) INTR pin tells about the end of the conversion
d) None of the mentioned
Explanation: CLK IN pin is used to tell about the conversion time, INTR pin tells about the end of the conversion and ADC0804 has a resolution of 8 bits only so all three statements are true.

4. While programming the ADC0808/0809 IC what steps are followed?
a) select the analog channel, start the conversion, monitor the conversion, display the digital results
b) select the analog channel, activate the ALE signal (L to H pulse), start the conversion, monitor the conversion, read the digital results
c) select the analog channel, activate the ALE signal (H to L pulse), start the conversion, monitor the conversion, read the digital results
d) select the channel, start the conversion, end the conversion
Explanation: While programming the ADC0808/0809 IC firstly we need to select the channel from the A, B, C pins. Then we need to activate the ALE signal, this is needed to latch the address. Then we start the conversion from the WR pin. After monitoring the INTR pin we get to know about the end of the conversion. Then we activate the OE enable to read out data out of the ADC chip.

5. In ADC0808/0809 IC which pin is used to select Step Size?
a) Vref
b) Vin
c) Vref/2 & Vin
d) None of the mentioned
Explanation: Step Size is calculated by formula Vref/(2n). As ADC0808/0809 8-bit ADC value of n=8. Therefore formula becomes Vref/(28) = Vref/256. If Vref = 5V then Step Size will be 5/256 i.e. 19.53mV.

6. What is the difference between ADC0804 and MAX1112?
a) ADC0804 has 8 bits and MAX1112 has 1 bit for data output
b) ADC0804 is used for adc and dac conversions whereas MAX1112 is used for serial data transmissions
c) ADC0804 has 32 bits and MAX1112 has 3 bit for data output
d) None of the mentioned

7. Which of the following statements are true about DAC0808?
a) parallel digital data to analog data conversion
b) it has current as an output
c) all of the mentioned
d) none of the mentioned
Explanation: DAC0804 is used for parallel data to analog data conversion.

8. 8 input DAC has ________
a) 8 discrete voltage levels
b) 64 discrete voltage levels
c) 124 discrete voltage levels
d) 256 discrete voltage levels
Explanation: For n input DAC has 2^n discrete voltage levels.

9. INTR, WR signal is an input/output signal pin?
a) both are output
b) both are input
c) one is input and the other is output
d) none of the mentioned
Explanation: INTR pin tells about the end of the conversion (output) and WR pin tells us to start the conversion (input).

10. What is the function of the SCLK pin in MAX1112?
a) It is used to bring data in
b) It is used to bring data out and send in the control byte, one at a time
c) It is used to get output clock
d) It is used to get serial output
Explanation: SCLK is used to bring data out and send in the control byte.

11. What is the principle on which electromagnetic relays operate?
a) electromagnetic induction
b) motor control
c) switching
d) none of the mentioned
Explanation: Electromagnetic relays work on the principle of electromagnetic induction. It is used as a switch in industrial controls, automobile and appliances. It allows the isolation of the sections of a system with two different voltage sources.

12. What are DPDT relays?
a) Single pole, single throw
b) Single pole, double throw
c) Double pole, double throw
d) None of the mentioned
Explanation: In DPDT relay, there are two poles and two throws (i.e.contacts). For each pole there are two contacts i.e. normally open (NO) and normally closed (NC). The contacts can be NO or NC. Generally, contact is NC when the coil is not energized. When the coil is energized both poles become NC.

13. Why do we need a ULN2803 in driving a relay?
a) for switching a motor
b) for increasing the current
c) for increasing the power
d) for switching the voltage
Explanation: We need a ULN2803 for driving a relay because the relay coil requires 10mA or more current to be energized. If microcontroller pins are not able to provide sufficient current to drive relays then we need ULN2803 for driving relays.

14. Why are solid-state relays advantageous over electromechanical relays?
a) they need zero voltage circuit
b) they need less current to be energised
c) they need less voltage to be energised
d) none of the mentioned
Explanation: Solid-state relays are advantageous over electromechanical relays because their switching response time is much faster than electromechanical relays as solid-state relays are made-up of semiconductor materials. Also, solid-state relays required low input current for operation and small packaging make them ideal for microcontrollers.

15. What are optoisolators?
a) it is a driver
b) it is a thing isolated from the entire world
c) it is a device that can be used as an electromagnetic relay without a driver
d) none of the mentioned
Explanation: Optoisolators are devices that can be used as an electromagnetic relay without a driver. It usually consists of a led (transmitter) and a photoresistive receiver.

16. How can we control the speed of a stepper motor?
a) by controlling its switching rate
b) by controlling its torque
c) by controlling its wave drive 4 step sequence
d) cant be controlled
Explanation: Speed of a stepper motor can be controlled by changing its switching speed or by changing the length of the time delay loop.

17. Which of the following can be a unit for torque?
a) kg/m2
b) ounce-inch
c) kg-m3
d) g/m
Explanation: Torque is equal to the force applied at a particular distance. So its unit can be ounce-inch.

18. The RPM rating given for the DC motor is for?
c) none of the mentioned
d) all of the mentioned
Explanation: RPM rating given for a DC motor is for a no-loaded condition.

19. How can we change the speed of a DC motor using PWM?
a) By changing amplitude of PWM
b) By keeping fixed duty cycle
c) By changing duty cycle of PWM
d) By increasing power of PWM
Explanation: We can change the speed of a DC motor using PWM by changing the duty cycle of PWM. Changing duty cycle means changing ON and OFF timing of PWM. Even if amplitude of PWM is fixed by increasing the ON time of PWM increases the speed of the DC motor.

20. How can the direction of the DC motor be changed?
a) by changing the torque
b) by changing the switching speed
c) by changing the polarity of voltages connected to the leads
d) by changing the RPM rating
Explanation: The direction of the DC motor can be changed by changing the polarity of the voltages connected to its leads.

21. How many rows and columns are present in a 16*2 alphanumeric LCD?
a) rows=2, columns=32
b) rows=16, columns=2
c) rows=16, columns=16
d) rows=2, columns=16
Explanation: 16*2 alphanumeric LCD has 2 rows and 16 columns.

22. How many data lines are there in a 16*2 alphanumeric LCD?
a) 16
b) 8
c) 1
d) 0
Explanation: There are eight data lines from pin no 7 to pin no 14 in an LCD.

23. Which pin of the LCD is used for adjusting its contrast?
a) pin no 1
b) pin no 2
c) pin no 3
d) pin no 4
Explanation: Pin no 3 is used for controlling the contrast of the LCD.

24. For writing commands on an LCD, RS bit is
a) set
b) reset
c) set & reset
d) none of the mentioned
Explanation: For writing commands on an LCD, RS pin is reset.

25. Which command of an LCD is used to shift the entire display to the right?
a) 0x1C
b) 0x18
c) 0x05
d) 0x07
Explanation: 0x1C is used to shift the entire display to the right.

26. Which command is used to select the 2 lines and 5*7 matrix of an LCD?
a) 0x01
b) 0x06
c) 0x0e
d) 0x38
Explanation: 0x38 is used to select the 2 lines and 5*7 matrix of an LCD.

27. Which of the following step/s is/are correct for sending data to an LCD?
a) set the R/W bit
b) set the E bit
c) set the RS bit
d) all of the mentioned
Explanation: To send data to an LCD, RS pin should be set so that LCD will come to know that it will receive data which has to display on the screen. R/W pin should be reset as data has to be displayed (i.e. write to the LCD). High to low pulse must be applied to the E pin when data is supplied to data pins of the LCD.

28. Which of the following step/s is/are correct to perform reading operation from an LCD?
a) low to high pulse at E pin
b) R/W pin is set high
c) low to high pulse at E pin & R/W pin is set high
d) none of the mentioned
Explanation: For reading operations, R/W pin should be made high and added to it, a low to high pulse is also generated at the E pin.

29. Which instruction is used to select the first row first column of an LCD?
a) 0x08
b) 0x0c
c) 0x80
d) 0xc0
Explanation: 0x80 is used to select the first row first column of an LCD.

30. The RS pin is _________ for an LCD.
a) input
b) output
c) input & output
d) none of the mentioned
Explanation: The RS pin is an input pin for an LCD.

31. In AVR, the LCD operates in two main modes, it can be in 8 bit or 4 bit data.
a) true
b) false
c) depends on the situation
d) can’t be said
Explanation: In AVR, the LCD operates in two main modes, they are in the 8 bit data transfer mode and the 4 bit data transfer mode.

32. What can be the sequence of commands that may be used for initializing an LCD?
a) 0x06, 0x0e, 0x01
b) 0x0e, 0x01, 0x80
c) 0x38, 0x0e, 0x01
d) all of the mentioned
Explanation: For initializing an LCD, we can use commands like 0x38 for selecting the 5*7 matrix, 0x0e for display on and the cursor blinking and 0x01 for clearing the screen.

33. When the LCD operates in the 4 bit mode, then what more commands are added to it?
a) 33
b) 32
c) 28
d) all of the mentioned
Explanation: When an LCD operates in the 4 bit mode than 33, 32, 28 in hex are sent to it. They represent 3, 3, 3, 2 nibbles which tell the LCD to do into the 4 bit mode for saving the i/o pins of the port.

34. What is the main function of the LPM instruction used in LCD?
a) for initializing the LCD in the read mode
b) for initializing the LCD in the write mode
c) for sending a long string of characters to the LCD
d) all of the mentioned
Explanation: LPM instruction is used for sending a long string of characters to the LCD.

35. The RS pin acts as an
a) input pin
b) output pin
c) any of the mentioned depending on the conditions
d) none of the mentioned
Explanation: The RS pin of the LCD is used for selecting a particular register used for sending a command or the data to the LCD.

36. To latch in information at the data pins of the LCD, we send
a) H-L pulse at the E pin
b) L-H pulse at the E pin
c) A constant H pulse at the E pin
d) A constant L pulse at the E pin
Explanation: For latching in information at the data pins of the LCD, we send a H-L pulse at the LCD.

37. What is the function of the 0x06 command?
a) to clear the LCD
c) to shift the cursor to the right
d) for selecting the matrix
Explanation: 0x06 command is used for shifting the cursor to the right after every data send to it.

38. What is the address of the second column and the second row of the 2*20 LCD?
a) 0x80
b) 0x81
c) 0xc0
d) 0xc1
Explanation: 0xc0 acts as the address for selecting the second row and the first column of the LCD, so according to it if we need to select the second row and the second column of the LCD, then the address should be 0xc1.

39. Which of the following commands takes more than 100 microseconds to run?
a) shift cursor left
b) shift cursor right
c) set address location of the DDRAM
d) clear screen
Explanation: Clear screen is a command that takes more than 100 microseconds to run.

40. For selecting the data pins in an LCD, RS pin should be
a) 1
b) 0
c) F
d) 10
Explanation: For selecting the data pins of the LCD, the RS pin of the LCD should be set to 1.

41. Which of the following steps detects the key in a 4*4 keyboard matrix about the key that is being pressed?
b) ensuring that initially, all keys are open
c) checking that whether the key is actually pressed or not
d) all of the mentioned
Explanation: For detecting that whether the key is actually pressed or not, firstly this must be ensured that initially all the keys are closed. Then we need to mask the bits individually to detect that which key is pressed. Then we need to check that is the key actually pressed or not, by checking that whether the key pressed for a time more than 20 micro seconds.

42. What is described by this command: CJNE A,#00001111b, ROW1
a) it masks the bit and then jumps to the label where ROW1 is written
b) it makes the value of the accumulator 0FH and then jumps at the address where ROW1 label is written
c) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the value becomes equal
d) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the value is not equal
Explanation: This particular command CJNE A,#00001111b, ROW1 compares the value of the accumulator with OFH and jumps to ROW1 address if the value is not equal.

43. To detect that in which column, the key is placed?
a) we can mask the bits and then check it
b) we can rotate the bits and then check that particular bit which is set or reset(according to the particular condition)
c) none of the mentioned
d) all of the mentioned
Explanation: We can mask or we can even rotate the bits to check that particularly in which column is the key placed.

44. In reading the columns of a matrix, if no key is pressed we should get all in binary notation
a) 0
b) 1
c) F
d) 7
Explanation: If no key is pressed, then all the keys show 1 as they are all connected to power supply.

45. If we need to operate a key of a keyboard in an interrupt mode, then it will generate what kind of interrupt?
a) ES
b) EX0/EX1
c) T0/T1
d) RESET
Explanation: If a key is to operate in an interrupt mode then it will generate an external hardware interrupt.

46. To identify that which key is being pressed, we need to:
a) ground all the pins of the port at a time
b) ground pins of the port one at a time
c) connect all the pins of the port to the main supply at a time
d) none of the mentioned
Explanation: To detect that which key is being pressed, we need to ground the pins one by one.

47. Key press detection and Key identification are:
a) the same processes
b) two different works are done in Keyboard Interfacing
c) none of the mentioned
d) any of the mentioned
Explanation: They are two different works that are involved in Keyboard Interfacing. One is used for checking that which key is being actually pressed and the other is used to check that is the key actually pressed or not.

48. The 8255 is a ______ chip.
a) Input/Output
b) Analog to Digital
c) Digital to analog
d) None of the mentioned
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used to expand the I/O ports of microcontrollers.

49. Which pins of a microcontroller are directly connected with 8255?
a) RD
b) WR
c) D0-D7
d) All of the mentioned
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control signals and also for transferring the data.

50. Find the control word for PA = out, PB = in, PCL = out, PCH = out (Mode0)?
a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all others as the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.

51. Which pins are used to select the ports and the control register?
a) CS
b) A1
c) A0
d) All of the mentioned
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are used for select ports and the control register.

52. What is the value of the control register when RESET button is set to zero?
a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET is activated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register remains the same as it is even when the RESET button is set to zero.

53. Why MOVX instruction is being used to access the ports of the 8255?
a) because 8255 is connecting a microcontroller in memory mapped I/O configuration
b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that memory space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to access external memory locations.

54. What is correct about the BSR mode from below?
a) In BSR mode, only the individual bits of PORT A can be programmed
b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
d) none of the mentioned
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.

55. How many pins of the 8255 can be used as the I/O ports?
a) 8
b) 16
c) 24
d) 32
Explanation: There are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.

#### Module 04

1. What is the processor used by ARM7?
a) 8-bit CISC
b) 8-bit RISC
c) 32-bit CISC
d) 32-bit RISC
Explanation: ARM7 is a group 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use.

2. What is the instruction set used by ARM7?
a) 16-bit instruction set
b) 32-bit instruction set
c) 64-bit instruction set
d) 8-bit instruction set
Explanation: ARM introduced the Thumb 16-bit instruction set providing improved code density compared to previous designs. The most widely used ARM7 designs implement the ARMv4T architecture, but some implement ARM3 or ARMv5TEJ.

3. How many registers are there in ARM7?
a) 35 register( 28 GPR and 7 SPR)
b) 37 registers(28 GPR and 9 SPR)
c) 37 registers(31 GPR and 6 SPR)
d) 35 register(30 GPR and 5 SPR)
Explanation: ARM7TDMI has 37 registers(31 GPR and 6 SPR). All these designs use a Von Neumann architecture, thus the few versions comprising a cache do not separate data and instruction caches.

4. ARM7 has an in-built debugging device?
a) True
b) False
Explanation: Some ARM7 cores are obsolete. It had a JTAG based on-chip debugging; the preceding ARM6 cores did not support it. The “D” represented a JTAG TAP for debugging.

5. What is the capability of ARM7 f instruction for a second?
a) 110 MIPS
b) 150 MIPS
c) 125 MIPS
d) 130 MIPS
Explanation: It is a versatile device for mobile devices and other low power electronics. This processor architecture is capable of up to 130MIPS on a typical 0.13 um process.

6. We have no use of having silicon customization?
a) True
b) False
Explanation: It achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extension, optimization for size, debug support, etc.

7. Which of the following has the same instruction set as ARM7?
a) ARM6
b) ARMv3
c) ARM71a0
d) ARMv4T
Explanation: The original ARM7 was based on the earlier ARM6 design and used the same ARM3 instruction set.

8. What are t, d, m, I stands for in ARM7TDMI?
a) Timer, Debug, Multiplex, ICE
b) Thumb, Debug, Multiplier, ICE
c) Timer, Debug, Modulation, IS
d) Thumb, Debug, Multiplier, ICE
Explanation: The ARM7TDMI(ARM7 + 16 bit Thumb + JTAG Debug + fast Multiplier + enhanced ICE) processor implements the ARM4 instruction set.

9. ARM stands for _________
Explanation: ARM, originally Acorn RISC Machine, later Advanced RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computing processors.

10. What are the profiles for ARM architecture?
a) A,R
b) A,M
c) A,R,M
d) R,M
Explanation: ARMv7 defines 3 architecture “profiles”:
A-profile, Application profile
R-profile, Real-time profile
M-profile, Microcontroller profile.

11. ARM7DI operates in which mode?
a) Big Endian
b) Little Endian
c) Both big and little Endian
d) Neither big nor little Endian
Explanation: Big Endian configuration, when BIGEND signal is HIGH the processor treats bytes in memory as being in Big Endian format. When it is LOW memory is treated as little Endian.

12. In which of the following ARM processors virtual memory is present?
a) ARM7DI
b) ARM7TDMI-S
c) ARM7TDMI
d) ARM7EJ-S
Explanation: ARM7DI is capable of running a virtual memory system. The abort input to the processor may be used by the memory manager to inform ARM7DI of page faults.

13. How many instructions pipelining is used in ARM7EJ-S?
a) 3-Stage
b) 4-Stage
c) 5-Stage
d)2-stage
Explanation: A five-stage pipelining is used, consisting of Fetch, Decode, Execute, Memory, and Writeback stages. A six-stage pipelining is used in Jazelle state, consisting of Fetch, Jazelle, Execute, Memory, and Writeback stages.

14. How many bit data bus is used in ARM7EJ-s?
a) 32-bit
b) 16-bit
c) 8-bit
d) Both 16 and 32 bit
Explanation: The ARM7EJ-s processor has a Von Neumann architecture. This feature is a single 32-bit data bus that carries both instructions and data. Only load, store, and swap instructions can access data from memory. Data can be 8- bit.

15. What is the cache memory for ARM710T?
a) 12Kb
b) 16Kb
c) 32Kb
d) 8Kb
Explanation: The ARM710T is a general purpose 32-bit microprocessor with 8Kb cache, enlarged write buffer and memory management unit combined in a single chip.

16. ARM stands for _____________
c) Artificial Running Machines
d) Aviary Running Machines
Explanation: ARM is a type of system architecture.

17. The main importance of ARM micro-processors is providing operation with ______
a) Low cost and low power consumption
c) Lower error or glitches
d) Efficient memory management
Explanation: The Stand alone feature of the ARM processors is that they’re economically viable.

18. ARM processors where basically designed for _______
a) Main frame systems
b) Distributed systems
c) Mobile systems
d) Super computers
Explanation: These ARM processors are designed for handheld devices.

19. The ARM processors don’t support Byte addressability.
a) True
b) False
Explanation: The ability to store data in the form of consecutive bytes.

20. The address space in ARM is ___________
a) 224
b) 264
c) 216
d) 232
Explanation: None.

21. The address system supported by ARM systems is/are ___________
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian
Explanation: The way in which, the data gets stored in the system or the way of address allocation is called as address system.

22. Memory can be accessed in ARM systems by __________ instructions.
i) Store
ii) MOVE
iv) arithmetic
v) logical
a) i, ii, iii
b) i, ii
c) i, iv, v
d) iii, iv, v
Explanation: None.

23. RISC stands for _________
a) Restricted Instruction Sequencing Computer
b) Restricted Instruction Sequential Compiler
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer
Explanation: This is a system architecture, in which the performance of the system is improved by reducing the size of the instruction set.

24. In the ARM, PC is implemented using ___________
a) Caches
b) Heaps
c) General purpose register
d) Stack
Explanation: PC is the place where the next instruction about to be executed is stored.

25. The additional duplicate register used in ARM machines are called as _______
a) Copied-registers
b) Banked registers
c) EXtra registers
d) Extential registers
Explanation: The duplicate registers are used in situations of context switching.

26. The banked registers are used for ______
a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
d) None of the mentioned
Explanation: When switching from one mode to another, instead of storing the register contents somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual registers.

27. Each instruction in ARM machines is encoded into __________ Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte
Explanation: The data is encrypted to make them secure.

28. All instructions in ARM are conditionally executed.
a) True
b) False
Explanation: None.

29. The addressing mode where the EA of the operand is the contents of Rn is ______
a) Pre-indexed mode
b) Pre-indexed with write back mode
c) Post-indexed mode
d) None of the mentioned
Explanation: None.

30. The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is _______
a) EA = [Rn]
b) EA = [Rn + Rm]
c) EA = [Rn] + Rm
d) EA = [Rm] + Rn
Explanation: Effective address is the address that the computer acquires from the current instruction being executed.

#### Module 05

1. In real time operating system ____________
a) all processes have the same priority
c) process scheduling can be done only once
d) kernel is not required

2. Hard real time operating system has ______________ jitter than a soft real time operating system.
a) less
b) more
c) equal
d) none of the mentioned
Explanation: Jitter is the undesired deviation from the true periodicity.

3. For real time operating systems, interrupt latency should be ____________
a) minimal
b) maximum
c) zero
d) dependent on the scheduling
Explanation: Interrupt latency is the time duration between the generation of interrupt and execution of its service.

4. In rate monotonic scheduling ____________
a) shorter duration job has higher priority
b) longer duration job has higher priority
c) priority does not depend on the duration of the job
d) none of the mentioned
Explanation: None.

5. In which scheduling certain amount of CPU time is allocated to each process?
b) proportional share scheduling
c) equal share scheduling
d) none of the mentioned
Explanation: None.

6. The problem of priority inversion can be solved by ____________
a) priority inheritance protocol
b) priority inversion protocol
c) both priority inheritance and inversion protocol
d) none of the mentioned
Explanation: None.

7. Time duration required for scheduling dispatcher to stop one process and start another is known as ____________
a) process latency
b) dispatch latency
c) execution latency
d) interrupt latency
Explanation: None.

8. Time required to synchronous switch from the context of one thread to the context of another thread is called?
b) jitter
c) context switch time
d) none of the mentioned
Explanation: None.

9. Which one of the following is a real time operating system?
a) RTLinux
b) VxWorks
c) Windows CE
d) All of the mentioned
Explanation: None.

10. VxWorks is centered around ____________
a) wind microkernel
b) linux kernel
c) unix kernel
d) none of the mentioned
Explanation: None.

11. Which module gives control of the CPU to the process selected by the short-term scheduler?
a) dispatcher
b) interrupt
c) scheduler
d) none of the mentioned
Explanation: None.

12. The processes that are residing in main memory and are ready and waiting to execute are kept on a list called _____________
a) job queue
c) execution queue
d) process queue
Explanation: None.

13. The interval from the time of submission of a process to the time of completion is termed as ____________
a) waiting time
b) turnaround time
c) response time
d) throughput
Explanation: None.

14. Which scheduling algorithm allocates the CPU first to the process that requests the CPU first?
a) first-come, first-served scheduling
b) shortest job scheduling
c) priority scheduling
d) none of the mentioned
Explanation: None.

15. In priority scheduling algorithm ____________
a) CPU is allocated to the process with highest priority
b) CPU is allocated to the process with lowest priority
c) Equal priority processes can not be scheduled
d) None of the mentioned
Explanation: None.

16. In priority scheduling algorithm, when a process arrives at the ready queue, its priority is compared with the priority of ____________
a) all process
b) currently running process
c) parent process
d) init process
Explanation: None.

17. Which algorithm is defined in Time quantum?
a) shortest job scheduling algorithm
b) round robin scheduling algorithm
c) priority scheduling algorithm
d) multilevel queue scheduling algorithm
Explanation: None.

18. Process are classified into different groups in ____________
a) shortest job scheduling algorithm
b) round robin scheduling algorithm
c) priority scheduling algorithm
d) multilevel queue scheduling algorithm
Explanation: None.

19. In multilevel feedback scheduling algorithm ____________
a) a process can move to a different classified ready queue
b) classification of ready queue is permanent
c) processes are not classified into groups
d) none of the mentioned
Explanation: None.

20. Which one of the following can not be scheduled by the kernel?
c) process
d) none of the mentioned
Explanation: User level threads are managed by thread library and the kernel is unaware of them.

21. What is Inter process communication?
a) allows processes to communicate and synchronize their actions when using the same address space
b) allows processes to communicate and synchronize their actions without using the same address space
c) allows the processes to only synchronize their actions without communication
d) none of the mentioned
Explanation: None.

22. Message passing system allows processes to __________
a) communicate with one another without resorting to shared data
b) communicate with one another by resorting to shared data
c) share data
d) name the recipient or sender of the message
Explanation: None.

23. Which of the following two operations are provided by the IPC facility?
a) write & delete message
c) send & delete message
Explanation: None.

24. Messages sent by a process __________
a) have to be of a fixed size
b) have to be a variable size
c) can be fixed or variable sized
d) None of the mentioned
Explanation: None.

25. The link between two processes P and Q to send and receive messages is called __________
d) all of the mentioned
Explanation: None.

26. Which of the following are TRUE for direct communication?
a) A communication link can be associated with N number of process(N = max. number of processes supported by system)
b) A communication link can be associated with exactly two processes
c) Exactly N/2 links exist between each pair of processes(N = max. number of processes supported by system)
d) Exactly two link exists between each pair of processes

Explanation: None.

27. In indirect communication between processes P and Q __________
a) there is another process R to handle and pass on the messages between P and Q
b) there is another machine between the two processes to help communication
c) there is a mailbox to help communication between P and Q
d) none of the mentioned
Explanation: None.

28. In the non blocking send __________
a) the sending process keeps sending until the message is received
b) the sending process sends the message and resumes operation
c) the sending process keeps sending until it receives a message
d) none of the mentioned
Explanation: None.

29. In the Zero capacity queue __________
a) the queue can store at least one message
c) the sender keeps sending and the messages don’t wait in the queue
d) none of the mentioned
Explanation: None.

30. The Zero Capacity queue __________
a) is referred to as a message system with buffering
b) is referred to as a message system with no buffering
c) is referred to as a link
d) none of the mentioned
Explanation: None.

31. Bounded capacity and Unbounded capacity queues are referred to as __________
a) Programmed buffering
b) Automatic buffering
c) User defined buffering
d) No buffering
Explanation: None.

32. Round robin scheduling falls under the category of ____________
a) Non-preemptive scheduling
b) Preemptive scheduling
c) All of the mentioned
d) None of the mentioned
Explanation: None.

33. With round robin scheduling algorithm in a time shared system ____________
a) using very large time slices converts it into First come First served scheduling algorithm
b) using very small time slices converts it into First come First served scheduling algorithm
c) using extremely small time slices increases performance
d) using very small time slices converts it into Shortest Job First algorithm
Explanation: All the processes will be able to get completed.

34. The portion of the process scheduler in an operating system that dispatches processes is concerned with ____________
a) assigning ready processes to CPU
b) assigning ready processes to waiting queue
c) assigning running processes to blocked queue
d) all of the mentioned
Explanation: None.

35. Complex scheduling algorithms ____________
a) are very appropriate for very large computers
b) use minimal resources
c) use many resources
d) all of the mentioned
Explanation: Large computers are overloaded with a greater number of processes.

36. What is FIFO algorithm?
a) first executes the job that came in last in the queue
b) first executes the job that came in first in the queue
c) first executes the job that needs minimal processor
d) first executes the job that has maximum processor needs
Explanation: None.

37. The strategy of making processes that are logically runnable to be temporarily suspended is called ____________
a) Non preemptive scheduling
b) Preemptive scheduling
c) Shortest job first
d) First come First served
Explanation: None.

38. What is Scheduling?
a) allowing a job to use the processor
b) making proper use of processor
c) all of the mentioned
d) none of the mentioned
Explanation: None.

39. There are 10 different processes running on a workstation. Idle processes are waiting for an input event in the input queue. Busy processes are scheduled with the Round-Robin time sharing method. Which out of the following quantum times is the best value for small response times, if the processes have a short runtime, e.g. less than 10ms?
a) tQ = 15ms
b) tQ = 40ms
c) tQ = 45ms
d) tQ = 50ms
Explanation: None.

40. Orders are processed in the sequence they arrive if _______ rule sequences the jobs.
a) earliest due date
b) slack time remaining
c) first come, first served
d) critical ratio
Explanation: None.

41. Which of the following algorithms tends to minimize the process flow time?
a) First come First served
b) Shortest Job First
d) Longest Job First
Explanation: None.

42. Under multiprogramming, turnaround time for short jobs is usually ________ and that for long jobs is slightly ___________
a) Lengthened; Shortened
b) Shortened; Lengthened
c) Shortened; Shortened
d) Shortened; Unchanged
Explanation: None.

43. Which of the following statements are true? (GATE 2010)

I. Shortest remaining time first scheduling may cause starvation
II. Preemptive scheduling may cause starvation
III. Round robin is better than FCFS in terms of response time

a) I only
b) I and III only
c) II and III only
d) I, II and III
Explanation: I) Shortest remaining time first scheduling is a preemptive version of shortest job scheduling. It may cause starvation as shorter processes may keep coming and a long CPU burst process never gets CPU.
II) Preemption may cause starvation. If priority based scheduling with preemption is used, then a low priority process may never get CPU.
III) Round Robin Scheduling improves response time as all processes get CPU after a specified time.

44. The time taken to respond to an interrupt is known as
a) interrupt delay
b) interrupt time
c) interrupt latency
d) interrupt function
Explanation: The interrupts are the most important function of the embedded system and are responsible for many problems while debugging the system. The time taken to respond to an interrupt is called the interrupt latency.

45. Into how many parts does the interrupt can split the software?
a) 2
b) 3
c) 4
d) 5
Explanation: The software interrupt can split into two parts. These are foreground work and background work.

46. Which of the following allows the splitting of the software?
a) wait statement
c) interrupt
d) acknowledgement
Explanation: The interrupt can make the software into two main parts and these are foreground work and background work.

47. Which part of the software is transparent to the interrupt mechanism?
a) background
b) foreground
c) both background and foreground
d) lateral ground
Explanation: The interrupt mechanism is transparent to the background software, that is, the background software is not aware of the existence of the foreground software.

48. Which part of the software performs tasks in response to the interrupts?
a) background
b) foreground
c) lateral ground
d) both foreground and background
Explanation: In the foreground work, the tasks are performed in response to the interrupts but in the background work, the tasks are performed while waiting for an interrupt.

49. In which of the following method does the code is written in a straight sequence?
a) method 1
b) timing method
c) sequence method
d) spaghetti method
Explanation: In the spaghetti method, the code is written in a straight sequence in which the analysis software goes and polls the port to see if there is data.

50. Which factor depends on the number of times of polling the port while executing the task?
a) data
b) data transfer rate
c) data size
d) number of bits
Explanation: The data transfer rate can determine the number of times the port is polled while executing the task.

51. Which of the following can improve the quality and the structure of a code?
a) polling
b) subroutine
c) sequential code
d) concurrent code
Explanation: The subroutine can improve the quality and the structure of the code. By using the polling method, as the complexity increases the software structure rapidly fall and it will become inefficient. So the subroutine method is adopted.

52. Which of the following are asynchronous to the operation?
a) interrupts
b) software
c) DMA
d) memory
Explanation: The interrupts are asynchronous to the operation and therefore can be used with systems that are the event as opposed to the time driven.

53. Which of the following can be used to create time-driven systems?
a) memory
b) input
c) output
d) interrupts
Explanation: The interrupts which are asynchronous can be used with systems that are the event as opposed to the time driven.

54. What does ISR stand for?
a) interrupt standard routine
b) interrupt service routine
c) interrupt software routine
d) interrupt synchronous routine
Explanation: The data transfer codes are written as part of the interrupt service routine which is associated with the interrupt generation by the hardware.

55. Which can activate the ISR?
a) interrupt
b) function
c) procedure
d) structure
Explanation: When the port receives the data, it will generate an interrupt which in turn activates the ISR.

56. Which code is written as part of the ISR?
b) sequential code
c) data transfer code
d) concurrent code
Explanation: The data transfer codes are written as part of the interrupt service routine which is associated with the interrupt generation by the hardware.

57. What is UNIX?
a) an operating system
b) a text editor
c) programming language
d) software program
Explanation: UNIX is an operating system developed in the early 1970’s at Bell Labs by Dennis Ritchie, Ken Thompson, and others. It is a multiuser, multitasking and timesharing operating system. The power of UNIX is derived from its commands and their multiple options.

58. In which language UNIX is written?
a) JAVA
b) Python
c) C++
d) C
Explanation: UNIX was originally written in Assembly language but Dennis Ritchie and Ken Thompson wanted an operating system which could run on more than one type of hardware. So in 1973, they rewrote the whole operating system in C language due to which one of the strongest features i.e. portability was added to the operating system.

59. Which of the following is not a feature of UNIX?
b) multiuser
c) portability
d) easy to use
Explanation: UNIX is a multitasking operating system i.e. a user can run multiple tasks concurrently. Similarly, it is a multiuser system because it permits working with multiple users on a single operating system. But a major disadvantage of UNIX lies in the fact that the richness provided by its commands requires a special type of commitment to understand the subject. i.e. the user must be well aware of commands he is using and the functions performed by them.

60. Which of the following is not a part of all the versions of UNIX?
a) Kernel and Shell
b) Commands and utilities
c) Graphical user interface
d) System Calls
Explanation: The kernel is the heart of the operating system while the shell is the utility which processes our requests. While system calls are a handful of functions which are used to interact with the kernel and make available the services provided by the operating system. A Graphical user interface (GUI) is available in UNIX, but the traditional UNIX interface is the command line only.

61. Which of the following is not true about UNIX?
a) Many people can use a UNIX based computer at the same time; hence UNIX is called as a multiuser system
b) A user can run multiple programs at the same time; hence UNIX is called a multitasking environment
c) UNIX was not written in ‘C’ language
d) Linux is also known as a version of UNIX
Explanation: One of the most attractive features of UNIX is that it supports multi-user and multitasking environment which makes it so popular among its users. There are many UNIX variants available in the market. Solaris Unix, AIX, HP Unix, BSD are some of the examples. Linux is also a flavor of UNIX which is freely available. Unix was developed in 1969 by AT&T employees Ken Thompson, Dennis Ritchie, Douglas McIlroy, and Joe Ossanna at Bell Labs and was written in ‘C’.

62. POSIX is a set of standards specified for establishing compatibility between operating systems.
a) True
b) False
Explanation: POSIX- Portable Operating System Interface for Computer Environment is basically a set of standards specified by IEEE for establishing compatibility between operating systems, especially which are UNIX based. For example, if we write a program relying on POSIX standards, we can easily port it among a large family of Unix derivatives (including Linux).

63. Shell is a command interpreter used for interacting with a UNIX system.
a) True
b) False
Explanation: Computers don’t have any capability of translating commands into actions. To do so we require shell-a command interpreter which translates our commands into actions. It is actually the interface between the user and kernel. There could be multiple shells in action on a single system.

64. Which part of the UNIX operating system interacts with the hardware?
a) Kernel
b) Shell
c) vi editor
d) application program
Explanation: The kernel is the core of the operating system. It is a collection of routines written in C which directly communicates with the hardware. User programs that need to interact with the hardware access the services of the kernel. There is only one kernel running on a system, unlike shells which can be multiple.

65. Two UNIX systems may or may not use the same set of system calls.
a) True
b) False
Explanation: All UNIX flavors have one thing in common, they use the same system calls which are described in POSIX specification.

66. What is a superuser?
a) system manager
b) normal user
d) a user with special rights
Explanation: A superuser (root) is the UNIX system manager which can perform special tasks like killing any executing program, resetting other users passwords, change users permissions and performing other system management tasks. The administrator can switch to superuser by issuing su command.

67. What is the windowing system of UNIX known as?
a) X Window system
b) LINUX
c) Red Hat
d) DOS
Explanation: The X window system, commonly known as X, is a windowing system developed at MIT. It is an open-source, network transparent, client-server based system that provides a Graphical user interface. X is primarily used on UNIX variants but it is also available for other operating systems also.

#### Module 06

1. How many types of arduinos do we have?
a) 5
b) 6
c) 8
d) 6
Explanation: There are 4 Arduino boards and 4 Arduino shields that fit on top of Arduino compatible boards to provide additional capability like connecting to the internet, motor controller, LCD screen controlling etc.,.

2. What is the microcontroller used in Arduino UNO?
a) ATmega328p
b) ATmega2560
c) ATmega32114
d) AT91SAM3x8E
Explanation: ATmega328p is a microcontroller which is 32KB of flash ROM and 8-bit microcontroller.

3. What does p refer to in ATmega328p?
a) Production
b) Pico-Power
c) Power-Pico
d) Programmable on chip
Explanation: Picopower technology employs advanced features like multiple clock domains, DMA and event systems to minimize power consumption.

4. Arduino shields are also called as _________
a) Extra peripherals
c) Connectivity modules
d) Another Arduinos
Explanation: The Arduino boards can connect with add- on modules termed as shields. Multiple, and possibly stacked shields may be individually addressable via an I2C serial bus.

5. What is the default bootloader of the Arduino UNO?
b) AIR-boot
c) Bare box
d) GAG
Explanation: The optiboot bootloader will take 512 bytes, leaving 32256 bytes for application code. Due to its small size larger up-loadable sketch size is achieved.

6. Does the level shifter converts the voltage levels between RS-232 and transistor-transistor logic.
a) True
b) False
Explanation: Level shifters are used in multi-design, different blocks work on different voltage levels. So when a signal passes from one voltage domain to another voltage this is needed particularly when a signal passes from low level to high level.

7. Which is the software or a programming language used for controlling of Arduino?
a) Assembly Language
b) C Languages
c) JAVA
d) Any Language
Explanation: A program for Arduino can be written in any programming language for a compiler that produces binary machine code for the target processor.

8. Do Arduino provides IDE Environment?
a) True
b) False
Explanation: It includes a code editor with features as texti cutting and pasting, searching and replacing text, automatic indenting, brace matching, syntax highlighting, and provides simple one-click mechanism to compile and uplaod programs to an Arduino board.

9. A program written with the IDE for Arduino is called _________
a) IDE source
b) Sketch
c) Cryptography
d) Source code
Explanation: Sketches are saved on the development computer as text files with the file extension .ino. Arduino software (IDE) pre-1.0 saved sketches with the extension file .pde.

10. Arduino IDE consists of 2 functions. What are they?
a) Build() and loop()
b) Setup() and build()
c) Setup() and loop()
d) Loop() and build() and setup()
Explanation: Setup() is called once in the program when a sketch starts after power-up. It is used to initialixe variables, input and output pin modes, and other libraries needed in the sketch.
Loop() is used after setup() been called, function loop() is executed repeatedly in the main program. It controls the board until the board is powered off or is reset.

11. How many digital pins are there on the UNO board?
a) 14
b) 12
c) 16
d) 20

Explanation: It has 14 digital pins input/output pins of which 6 can be used as PWM output, 6 analog inputs, a USB connection, a power jack, a reset button and more.

12. _________ board allows sewn into clothing.
a) UNO
b) RedBoard
d) Mega
Explanation: LilyPad was creatively designed with large connecting pads and a flat back to allow them to be sewn into clothing with conductive thread.

13. How many analog pins are used in Arduino Mega board?
a) 16
b) 14
c) 12
d) 8
Explanation: It has lots of digital input/output pins, 14 can be used as PWM output 16 analog inputs, a USB connection, a power jack, and a reset button.

14. Which board is first to use microcontroller within build USB?
b) UNO
c) RedBoard
d) Leonardo
Explanation: The Leonard is Arduino’s first development board to use one microcontroller with built-in USB. This means that it can be cheaper and simple, And also, code libraries are available which allow the board to emulate a computer keyboard etc.

15. ___________ are pre built circuit boards that fit on top of Android.
a) Sensor
b) Data types
d) Sheilds
Explanation: Shields are pre- built circuit boards that fit on top of board and provide additional capabilities like controlling motors, connecting to internet, providing cellular etc.

16. Does Raspberry Pi need external hardware?
a) True
b) False
Explanation: The RPi can be used without additional hardware (except perhaps a power supply of some kind), it won’t be much use as a general computer. As with any normal PC, it is likely you need some additional hardware.

17. Does RPi have an internal memory?
a) True
b) False
Explanation: The RPi has no internal storage or built-in operating system it requires an SD-card that is set up to boot the RPi.

18. What do we use to connect TV to RPi?
a) Male HDMI
b) Female HDMI
Explanation: HD TV’s and most LCD Monitors can be connected using a full-size male HDMI cable, and with an inexpensive adapter if DVI is used. HDMI version 1.4 cable is recommended.

19. How power supply is done to RPi?
a) USB connection
b) Internal battery
c) Charger
Explanation: The unit uses a Micro USB connection to power itself (only the power pins are connected so it will not transfer data over the connection). A standard modern phone charger with a micro USB connector will do, but needs at least 700 mA at 5 volts.

20. What is the Ethernet/LAN cable used in RPi?
a) Cat5
b) Cat5e
c) Cat6
d) RJ45
Explanation: We can use an Ethernet cable or a USB Wifi adapter. The RPi ethernet port is auto-sensing which means that it may be connected to a router or directly to another computer (without the need for a crossover cable).

21. What are the parameters that are default values?
a) Port_Name and Bits
b) Speed and Port_Names
c) Speed and Parity
d) Stop bit and Flow Control
Explanation: Port_Name: Linux automatically assigns different names for different types of serial connectors. For Standard Serial Port: ttyS0 … ttySn
USB Serial Port Adapter: ttyUSB0 … ttyUSBn
Speed: 115200.

22. What is the command used for easy using of GNU screen?
b) Screen Port_Name115200
c) Minicom -b 115200 -o -D Port_Name
d) Prompt> # help
Explanation: This command is used to open and write or modify data on GNU screen and we should write in the terminal window.

23. Which instruction set architecture is used in Raspberry Pi?
a) X86
b) MSP
c) AVR
d) ARM
Explanation: ARM assembler is used in Raspberry Pi. Machine language is built up from discrete statements or instructions implemented by a particular processor.

24. What is the default user in Debain on Raspberry Pi?
a) Default
b) User
c) Pi
d) Root
Explanation: Linux users. User management in Raspberry is done on the command line. The default user is Pi, and the password is raspberry. You can add users and change each user’s password.

25. What are the distributions are supported by raspberry Pi?
a) Arch Linux
b) Debain
c) Fedora Remix
d) Arch Linux, Debain, and Fedora Remix
Explanation: These all are the distributors that have Linux operating system which has default GUI for Fedora as Xfce, Mate, None-depends on spin.

26. What bit processor is used in Pi 3?
a) 64-bit
b) 32-bit
c) 128-bit
d) Both 64 and 32 bit
Explanation: The first is a next generation Quad Core Broadcom BCM2837 64-bit ARMv8 processor, making the processor speed increase from 900MHz on the Pi 2 to up to 1.2GHz on the Pi 3.

27. What is the speed of operation in Pi 3?
a) 900MHz
b) 1.2GHz
c) 1GHz
d) 500MHz
Explanation: The first is a next generation Quad Core Broadcom BCM2837 64-bit ARMv8 processor, making the processor speed increase from 900MHz on the Pi 2 to up to 1.2GHz on the Pi 3.

28. WiFi is not present in which of the following models?
a) Raspberry Pi3
b) Raspberry Pi Zero WH
c) Raspberry Pi Zero W
d) Raspberry Pi Zero
Explanation: All the 3 has an inbuilt Wifi in which all of them works on 802.11 n. For Raspberry Pi Zero an external ESP2866 should be connected.

29. Does micro SD card present in all modules?
a) True
b) False
Explanation: All the products have an inbuilt memory as well as an extended memory.

30.How many USB ports are present in Raspberry Pi 3?
a) 5
b) 2
c) 4
d) 3
Explanation: In Raspberry Pi3 there is an upgraded switched power source that goes up to 2.5 Amps instead of just 2 Amps, allowing pi to power even more powerful devices over USB ports.

31. Galileo Gen 2 board was developed by which company?
a) Atmel
b) Intel
c) Motorola
d) Dallas
Explanation: Intel Galileo is the first in the line of boards based on intelx86 architecture and is designed for education communities.

32. Galileo gen 2 board is some time called as Breakout Board?
a) True
b) False
Explanation: It is named as Breakout Boards.

33. Intel Galileo has the main feature of?
a) Support PCI Express
b) Intel Quart
c) Support for openCV
d) Onboard real time clock
Explanation: Intel Galileo features the Intel quart SoC X1000, the first product from the Intel Quart technology family of low power, small-core products. Intel Quart represents Intel’s attempt to compete within markets such as the Internet of Things and Wearable Computing.

34. Which among the following is more powerful?
a) Rasberry Pi 2 Model
b) Rasberry Pi 3 Model
c) Galieo Gen 2 Board
d) Galieo Gen 1 Board
Explanation: The latest iteration, the Pi 3 Model B, replaced the PI 2 Model B. It is more powerful than the older Galieo Gen 2, featuring a 1.2 GHz CPU and 1 Gb RAM. The Pi, however, does not have any flash memory.

35. Periferal Component Interconnect (PCI) Express interconnects which modules?
a) Serial communication
b) WIfi, Bluetooth, GSM cards
c) Micro SD card
d) Real Time Clock
Explanation: PCI is a high speed serial computer expansion bus standard. It includes higher maximum system bus throughput, lower I/O pin count and smaller physical footprint.

36. What is the frequency of the Galileo gen 2 board?
a) 250MHz
b) 400MHz
c) 450MHz
d) 300MHz
Explanation: The frequency of the board gives the speed of operation of board. So, increase in frequency increases the speed.

37. The 10/100Mbit Ethernet support enables the board to connect to _________
a) LAN
b) MAN
c) WAN
d) WLAN
Explanation: The 10/100 Mbit Ethernet support enables the board to be connected to a LAN. It also enables to accessing the linux shell.

38. What is the range of microSD card that is connected externally?
a) 16GB
b) 32Gb
c) 8Gb
d) 64Gb
Explanation: The external Micro SD card has a range of 32Gb.

39. Which of the following has a real time clock?
a) Galileo Gen 2
b) Rasberry Pi
c) Arduino
d) Rasberry Pi 3
Explanation: The Rasberry Pi, as well as most Arduino, does not have an on board real time clock. The Galileo boards have a real time clock, requiring only a 3V coin cell battery. The boards can therefore keep accurate time without being connected to either a power source or internet.

40. Which bus is a standard bus derived by ARM with aim to support efficient on chip?
a) Serial Attached SCSI
b) Futurebus
d) Scalable Coherent Interface
Explanation: AMB is used for simple cost effective design transfer, pipelined transfer operation, and multiple bus masters. It is known for high performance and high clock synthesizable design, providing high bandwidth channel between processor and peripherals.

41. How many digital I/O pins are there in Board?
a) 29
b) 15
c) 25
d) 20
Explanation: Android compatible header containing 20 digital I/O pins in which 12 are fully native speed.

42. Does the board has UART?
a) True
b) False
Explanation: Galileo Gen 2 board has 2 UARTs, one shared with console UART. Serial console UART header is compatible with FTDI USB converter.

43. What is the storage memory of EEPROM?
a) 16kb
b) 6kb
c) 8kb
d) 12kb

Explanation: The EEPROMs memory is 8kb while it has external SD card option of 32GB.

44. What is the USB version that is supported?
a) USB 4.0
b) USB 1.5
c) USB 3.0
d) USB 2.0
Explanation: In addition to android hardware and software compatibility, the Intel Galileo board includes the following industry standards I/O ports and features: USB 2.0 Host port and USB 2.0 Client port.

45. ________ bit PWM for more precise control of servos and smoother response.
a) 14-bit
b) 12-bit
c) 8-bit
d) 6-bit
Explanation: 12-bit PWM for more precise control of servos and smoother response.

46. A software that can be freely accessed and modified.
a) Synchronous Software
b) Package Software
c) OSS
d) Middleware
Explanation: Software refers to a collection of programs. OSS stands for Open Source Software. It can be freely accessed, edited and modified according to our needs.

47. Open Source Software can be used for commercial purpose.
a) True
b) False
Explanation: The statement is true. The definition of open source guarantees the use of open source software for commercial purposes. It is commercial but not proprietary.

48. PNG is a _________
a) image format
b) file format
c) internet format
d) html format
Explanation: PNG is an image format. It stands for portable network graphics. PNG supports palette based images.

49. OSI stands for?
a) Open Source Index
b) Open Source Image
c) Open Source Initiative
d) Open Source Instant
Explanation: OSI is open source initiative. It is a leading authority on OSS. OSS is a computer software distributed along with its source code.

50. Which of the following is not an open source software?
a) LibreOffice
b) Microsoft Office
c) GNU image manipulation
d) MySQL
Explanation: MS-office is not open source software since its source code isn’t shared publicly. Others like Libre office, MySQL are open source softwares through which is distributed along with its source code.

51. The users must agree to the _______ terms and agreements when they use an open source software.
a) System
c) Community
d) Programmer
Explanation: The users must agree to the license terms and agreement in order to access an open source software. There is a limitation of OSS that the users cannot modify the terms and conditions of any software.

52. Which of the following is not a downside of OSS?
a) Lack of personalized support
b) Restricted choice
c) No warranty
d) Multiple choices
Explanation: An OSS is nothing but an open source software. It has restricted choices, i.e., there are fewer choices available for open source. Also, speed of change is an important downside, since the software keeps on updating itself, we cannot ensure if it is compatible with other applications.

53. An example of a web design OSS.
a) Nvu
b) KOffice
c) AbiWorld
d) Open Office
Explanation: Nvu is an example of an open source software for web designing. Others like KOffice, Open Office and AbiWorld are OSS examples for Office Automation.

54. An image editor similar to Adobe Photoshop.
a) Nvu
b) Open Office
c) Bluefish
d) GIMPshop
Explanation: GIMPshop is an image editor similar to adobe photoshop. Nvu is intended for those with no technical expertise.

55. An OSS for communication purpose.
a) Virtue Mart
b) Drupal
c) Pidgin
d) ZenCart
Explanation: Pidgin is used for Free Instant Messaging(IIM) client. Virtue mart and emart are for e-commerce purpose. Drupal is for content management.

56. Which of the following is correct about the word sensors?
a) that senses something
b) it is a type of a transducer that converts one form of energy to another
c) it can produce output in the form of electrical pulses, current or voltage
d) all of the mentioned
Explanation: Sensors are the devices that are used to sense a particular thing by converting one form of energy into another, this converted form can be in the form of some analog output, or in the form of current or the voltage as the case may be.

57. Why do we need to apply the concept of signal conditioning to a sensor?
a) in order to convert it into a desirable form of energy
b) for testing
c) for sensing something
d) all of the mentioned
Explanation: Signal Conditioning is the concept that is used for data acquisition of the signal. For measuring and analyzing this value at a practical stage, by converting it into a desirable form of energy.

58. Which of the following is correct about LM35 based sensors?
a) its output voltage is directly proportional to the Celsius scale
b) its output voltage is directly proportional to the Fahrenheit scale
c) none of the mentioned
d) all of the mentioned
Explanation: LM35 based sensors are those sensors whose output voltage is directly proportional to the Celsius scale.

59. What is the difference between the LM34 and the LM35 based sensors?
a) one requires external calibration while other does not
b) one has output voltage proportional to the Celsius scale while others have to the Fahrenheit scale
c) one is fast other is slow
d) all of the mentioned
Explanation: LM35 has the output voltage proportional to the Celsius scale while the LM35 based sensors have output voltage proportional to the Fahrenheit scale.

60. Every transducer must be connected with the signal conditioning circuit?
a) true
b) false
c) can’t say
d) depends on the conditions
Explanation: For analyzing purposes, every transducer must be connected to a signal conditioning circuit in order to measure its value as a practical platform.

61. LM35 provides _______ V for each degree count?
a) 1
b) 0.1
c) 0.001
d) 10
Explanation: LM35 provides 10mV for every degree change of the Celsius scale.

62. Why for the 8 bit analog input we select Vref as the 2.56V?
a) to obtain each degree count as the 2.56V
b) to get 2.56V at the output
c) to obtain each degree count as the 10mV
d) to get 10mV as the output
Explanation: For an 8 bit analog input, each degree count is calculated as the Vref/256, so if Vref is selected as 2.56V then we can obtain 10mV for each degree count of the scale.

63. What is the temperature for LM35 sensor if the analog output is 0011 1001?
a) 3
b) 9
c) 57
d) 41
Explanation: The binary for the above output is 57, so in case of LM35 sensors we obtain the output as 57 C.

64. In an external hardware, there are how many pins available for the LM35 and the LM34 based sensors?
a) 2
b) 3
c) 10
d) 1
Explanation: LM35 consists of mainly 3 pins, they are Vcc, Gnd, analog output.

65. Do LM34 and LM35 based sensors have linear output?
a) yes
b) no
c) depends on the conditions
d) can’t say