1. Which type of memory can read data but can’t write data?
a. Random only memory
b. Random-access memory
c. Read-only memory
d. None of the above
Answer :
C

2. Which type of memory can speed up computer processing?
a. ROM
b. Cache memory
c. Registers
d. Both A & B
Answer
B

3.Which one is volatile?
a. DROM
b. Secondary memory
c. RAM
d. Random Only memory
Answer
C

4.Which memory is onboard storage?
a. Random-access memory
b. Cache memory
c. Virtual memory
d. Random Only memory
Answer
B

5. From where the processor can access data fastly?
a. Random-access memory
b. Cache memory
c. Registers
d. Secondary memory
Answer
C

6. Which type of ROM contains no Initial storage at the time of manufacturing?
a. PROM
b. EROM
c. DROM
d. Both A&B
Answer
A

7. Which one is not known as type of computer memory?
a. DRAM
b. SRAM
c. FRAM
d. EPROM
Answer
C

8.How many bits contains by Cells of computer memory?
a. 16 Bits
b. 32 Bits
c. 4 Bits
d. 8 Bits
Answer
D

9. Which memory is necessary to refresh many times in one second?
a. Dynamic RAM
b. Static RAM
c. EPROM
d. ROM
Answer
A

10. RAM of a computer is
a. External Memory
b. Internal Memory
c. Auxiliary
d. None of the Above
Answer
B

11.Flash memory is Also Known as……………
a. Flash RAM
b. Flash ROM
c. Flash DROM
d. Flash SRAM
Answer
A

12.Primary memory is used for storing…………….
a. Data only
b. Calculations only
c. Programs only
d. All of the Above
Answer
D

13.The size of primary memory of computer in between
a. 2KB & 8KB
b. 8KB & 64KB
c. 64KB & 256KB
d. 256KB & 640KB
Answer
D

14.Memory is a part of
a. Input device
b. Output device
c. Central processing Unit
d. Control Unit
Answer
C

15.Whic one is ROM storage device?
a. Floppy disk
b. USB Device
c. Hard Disk
d. CD-ROM
Answer
D

16. Storage which stores or retains data after power off is called-
a. Volatile storage
b.Non-volatile storage
c.Sequential storage
d.Direct storage
e.None of these
Answer
B

17. A permanent memory, which halls data and instruction for start-up the computer and does not erase data after power off.
a. Network interface card
b.CPU
c.RAM
d.ROM
e.None of these
Answer
D

18. Which of the following memories must be refreshed many times per second?
a. EPROM
b.ROM
c.Static RAM
d.Dynamic RAM
Answer
D

19.USB-type storage device is –
a. Secondary
b.Axillary
c.Tertiary
d.Primary
Answer
A

20. Which of the following places the common data elements in order from smallest to largest?
a. Character, File, Record, Field, Database, File
b.Character, Record, Field, Database, File
c.Character, Field, Record, File, Database
d.Bit, Byte, Character, Record, Field, File, Database
e.None of these
Answer
C

21. Which device is used to back up the data?
a. Floppy Disk
b.Tape
c.Network Drive.
d.All of the above
e.None of these
Answer
D

22. A half byte is known as_____.
a. data
b.bit
c.half byte
d.nibble
e.None of these
Answer
D

23. Main memory of computer is –
a. Internal
b.External
c.a. and b.both
d.Auxiliary
e.None of these
Answer
A

24. The contents of memory into blocks of the same size is called as:
(A) ROM
b.EPROM
c.EEPROM
d.All of above
Answer
D

25. What is the permanent memory built into your computer called?
a. RAM
b.ROM
c.CPU
d.CD-ROM
e.None of these
Answer
B

26. What is the high speed memory between the main memory and the CPU called?
a) Register Memory
b) Cache Memory
c) Storage Memory
d) Virtual Memory
Answer: b
Explanation: It is called the Cache Memory. The cache memory is the high speed memory between the main memory and the CPU.

27. Cache Memory is implemented using the DRAM chips.
a) True
b) False
Answer: b
Explanation: The Cache memory is implemented using the SRAM chips and not the DRAM chips. SRAM stands for Static RAM. It is faster and is expensive.

28. Whenever the data is found in the cache memory it is called as _________
a) HIT
b) MISS
c) FOUND
d) ERROR
Answer: a
Explanation: Whenever the data is found in the cache memory, it is called as Cache HIT. CPU first checks in the cache memory since it is closest to the CPU.

29. LRU stands for ___________
a) Low Rate Usage
b) Least Rate Usage
c) Least Recently Used
d) Low Required Usage
Answer: c
Explanation: LRU stands for Least Recently Used. LRU is a type of replacement policy used by the cache memory.

30. When the data at a location in cache is different from the data located in the main memory, the cache is called _____________
a) Unique
b) Inconsistent
c) Variable
d) Fault
Answer: b
Explanation: The cache is said to be inconsistent. Inconsistency must be avoided as it leads to serious data bugs.

31. Which of the following is not a write policy to avoid Cache Coherence?
a) Write through
b) Write within
c) Write back
d) Buffered write
Answer: b
Explanation: There is no policy which is called as the write within policy. The other three options are the write policies which are used to avoid cache coherence.

32. Which of the following is an efficient method of cache updating?
a) Snoopy writes
b) Write through
c) Write within
d) Buffered write
Answer: a
Explanation: Snoopy writes is the efficient method for updating the cache. In this case, the cache controller snoops or monitors the operations of other bus masters.

33. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
a) Associative
b) Direct
c) Set Associative
d) Indirect
Answer: a
Explanation: This happens in the associative mapping. In this case, a block of data from the main memory can be mapped anywhere in the cache memory.

34. The number of sign bits in a 32-bit IEEE format is ____
a) 1
b) 11
c) 9
d) 23
Answer: a
Explanation: There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.

35. The transfer between CPU and Cache is ______________
a) Block transfer
b) Word transfer
c) Set transfer
d) Associative transfer
Answer: b
Explanation: The transfer is a word transfer. In the memory subsystem, word is transferred over the memory data bus and it typically has a width of a word or half-word.

1. 8051 microcontrollers are manufactured by which of the following companies?
a) Atmel
b) Philips
c) Intel
d) All of the mentioned
Answer: d
Explanation: 8051 microcontrollers are manufactured by Intel, Atmel, Philips/Signetics, Infineon, Dallas Semi/Maxim.

2. AT89C2051 has RAM of:
a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
Answer: a
Explanation: It has 128 bytes of RAM in it.

3. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0
Answer: a
Explanation: It has two 16 bit registers DPTR and PC.

4. When 8051 wakes up then 0x00 is loaded to which register?
a) PSW
b) SP
c) PC
d) None of the mentioned
Answer: c
Explanation: When 8051 wakes up, Program Counter (PC) loaded with 0000H. Because of this in 8051 first opcode is stored in ROM address at 0000H.

5. When the microcontroller executes some arithmetic operations, then the flag bits of which register are affected?
a) PSW
b) SP
c) DPTR
d) PC
Answer: a
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow, parity, register bank select bits etc which are affected during such operations.

6. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Answer: b
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and AC are set to 1. In the result, the number of 1’s present are even so parity flag is set to zero.

7. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
Answer: d
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2 RS1=1 and RS0=0 which are fourth and third bit of the register respectively.

8. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
d) none of the mentioned
Answer: a
Explanation: If we push elements onto the stack then the stack pointer increases with every push of element.

9. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Answer: b
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.

10. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Answer: c
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.

11. When an interrupt is enabled, then where does the pointer moves immediately after this interrupt has occurred?
a) to the next instruction which is to be executed
b) to the first instruction of ISR
c) to a fixed location in memory called interrupt vector table
d) to the end of the program
Answer: c
Explanation: When an interrupt occurs, then it jumps to a fixed memory location in memory called the interrupt vector table that holds the address of the Interrupt Service Routine.

12. What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?
a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
Answer: b
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be disabled or the contents of the IE register becomes null.

13. After RETI instruction is executed then the pointer will move to which location in the program?
a) next interrupt of the interrupt vector table
b) immediate next instruction where interrupt is occurred
c) next instruction after the RETI in the memory
d) none of the mentioned
Answer: b
Explanation: When the RETI instruction is executed, PC will fetch 2-bytes (address) from top of stack which is stored when interrupt is occurred. This will return to the place where interrupt is occurred and starts executing instructions.

14. Which pin of the external hardware is said to exhibit INT0 interrupt?
a) pin no 10
b) pin no 11
c) pin no 12
d) pin no 13
Answer: c
Explanation: INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled with a low leveled pulse.

15. Which bit of the IE register is used to enable TxD/RxD interrupt?
a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
Answer: d
Explanation: IE.D4 is used to enable RS interrupt or the serial communication interrupt.

16. Which of the following combination is the best to enable the external hardware interrupt 0 of the IE register (assuming initially all bits of the IE register are zero)?
a) EX0=1
b) EA=1
c) any of the mentioned
d) EX0=1 & EA=1
Answer: d
Explanation: For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is set to enable all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and mask the other enabled interrupts.

17. Why normally LJMP instructions are the topmost lines of the ISR?
a) so as to jump to some other location where there is a wider space of memory available to write the codes
b) so as to avoid overwriting of other interrupt instructions
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: There is a small space of memory present in the vector table between two different interrupts so in order to avoid overwriting of other interrupts we normally jump to other locations where a wide range of space is available.

18. Which register is used to make the interrupt level or an edge triggered pulse?
a) TCON
b) IE
c) IPR
d) SCON
Answer: a
Explanation: TCON register is used to make any interrupt level or edge triggered.

19. What is the disadvantage of a level triggered pulse?
a) a constant pulse is to be maintained for a greater span of time
b) another interrupt may be generated if the low-level signal is not removed before the ISR is finished
c) it is difficult to produce
d) another interrupt may be caused if the signal is still low before the completion of the last instruction
Answer: d
Explanation: In a level triggered interrupt, if the low signal at interrupt pin must be removed before the execution of last instruction of the ISR i.e. RETI. If low signal at interrupt pin is not removed before completing the ISR then it will be generating another interrupt.

20. What is the correct order of priority that is set after a controller gets reset?
a) RI/TI > TF1 > TF0 > INT1 > INT0
b) RI/TI < TF1 < TF0 < INT1 < INT0
c) INT0 > TF0 > INT1 > TF1 > RI/TI
d) INT0 < TF0 < INT1 < TF1 < RI/TI
Answer: c
Explanation: On reset Interrupt Priorities are as INT0 > TF0 > INT1 > TF1 > RI/TI, where ‘>’ is used to denote highest priority.

21. What is the clock source for the timers?
a) some external crystal applied to the micro-controller for executing the timer
b) from the crystal applied to the micro-controller
c) through the software
d) through programming
Answer: b
Explanation: Timer’s clock source is the crystal that is applied to the controller.

22. What is the frequency of the clock that is being used as the clock source for the timer?
a) some externally applied frequency f’
b) controller’s crystal frequency f
c) controller’s crystal frequency /12
d) externally applied frequency/12
Answer: c
Explanation: The frequency of the clock source for the timer is equal to f/12(where f is the frequency of the crystal).

23. What is the function of the TMOD register?
a) TMOD register is used to set various operation modes of timer/counter
b) TMOD register is used to load the count of the timer
c) Is the destination or the final register where the result is obtained after the operation of the timer
d) Is used to interrupt the timer
Answer: a
Explanation: TMOD is used to set various operation modes of timer/counter by the programmer.

24. What is the maximum delay that can be generated with the crystal frequency of 22MHz?
a) 2978.9 sec
b) 0.011 msec
c) 11.63 sec
d) 2.97 msec
Answer: d
Explanation: For generating the maximum delay we have to multiply the maximum number of counts with the time period required to execute one machine cycle( 65536*1/22MHz).

25. Auto reload mode is allowed in which mode of the timer?
a) Mode 0
b) Mode 1
c) Mode 2
d) Mode 3
Answer: c
Explanation: Auto reload is allowed in the Mode 2 of the timer because here in this mode, we don’t need to load the count again and again in the register.

26. Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2?
a) 00FFH,0FFFH,FFFFH
b) 1FFFH,0FFFH,FFFFH
c) 1FFFH,FFFFH,00FFH
d) 1FFFH,00FFH,FFFFH
Answer: c
Explanation: For Mode 0 13 bit value is used so 1FFFH is chosen to be the roll over value. Similarly for Mode 1 FFFFH and for Mode 2 FFH is the roll over value for the timers and counter.

27. What steps are followed when we need to turn on any timer?
a) load the count, start the timer, keep monitoring it, stop the timer
b) load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer
c) load the TMOD register, start the timer, load the count, keep monitoring it, stop the timer
d) none of the mentioned
Answer: b
Explanation: When any timer is to turn on, then firstly we have to load the TMOD register and the count. Then the timer is to get started. After then, we need to monitor the timer properly and then when the roll over condition arises then the timer is to be stopped.

28. If Timer 0 is to be used as a counter, then at what particular pin clock pulse need to be applied?
a) P3.3
b) P3.4
c) P3.5
d) P3.6
Answer: b
Explanation: If Timer 0 is to be used as a counter, then a pulse has to be applied at P3.4 and if it is for Timer 1 then the clock pulse has to be applied at the pin P3.5.

29. In the instruction “MOV TH1,#-3”, what is the value that is being loaded in the TH1 register?
a) 0xFCH
b) 0xFBH
c) 0xFDH
d) 0xFEH
Answer: c
Explanation: Negative value is loaded in 2’s complement form. -3 represented in 2’s complement form as FDH.
Steps to convert into 2’s complement:
3 → 0000 0011 Binary Equivalent of ‘3’
→ 1111 1100 1’s Complement of decimal ‘-3’
→ 1111 1101 2’s Complement of decimal ‘-3’
F D Hex Equivalent of ‘-3’

30. TF1, TR1, TF0, TR0 bits are of which register?
a) TMOD
b) SCON
c) TCON
d) SMOD
Answer: c
Explanation: All of these bits are part of TCON (Timer Control) register. TF0 and TF1 are used to check overflow of timer 0 and timer 1 respectively. TR0 and TR1 are timer control bits used to start and stop of timer 0 and timer 1 respectively.

31. Which devices are specifically being used for converting serial to parallel and from parallel to serial respectively?
a) timers
b) counters
c) registers
d) serial communication
Answer: c
Explanation: Some registers like the parallel in serial out and serial in parallel out are used to convert serial data into parallel and vice versa respectively.

32. What is the difference between UART and USART communication?
a) they are the names of the same particular thing, just the difference of A and S is there in it
b) one uses asynchronous means of communication and the other uses synchronous means of communication
c) one uses asynchronous means of communication and the other uses asynchronous and synchronous means of communication
d) one uses angular means of the communication and the other uses linear means of communication
Answer: c
Explanation: UART stands for Universal Asynchronous receiver-transmitter and USART stands for Universal Synchronous and Asynchronous receiver-transmitter.

33. Which of the following best describes the use of framing in asynchronous means of communication?
a) it binds the data properly
b) it tells us about the start and stops of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control
Answer: b
Explanation: In data framing in asynchronous means of communication, the data is packed between the start and the stop bit. This is done so as to tell the other computer about the start and the end of the data.

34. Which of the following signal control the flow of data?
a) RTS
b) DTR
c) RTS & DTR
d) None of the mentioned
Answer: a
Explanation: RTS is a request to send control signal which is a control for the flow of data. On the other hand DTR is a Data Terminal Ready control signal which tells about the current status of the DTE.

35. Which of the following is the logic level understood by the micro-controller/micro-processor?
a) TTL logic level
b) RS232 logic level
c) None of the mentioned
d) TTL & RS232 logic level
Answer: a
Explanation: TTL logic or the transistor logic level is the logic that is understood by the micro-controllers/microprocessors.

36. What is a null modem connection?
a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication
Answer: c
Explanation: In null modem connection the RxD of one is the TxD for the other.

37. Which of the following best states the reason that why baud rate is mentioned in serial communication?
a) to know about the no of bits being transmitted per second
b) to make the two devices compatible with each other, so that the transmission becomes easy and error free
c) to use Timer 1
d) for wasting memory
Answer: b
Explanation: To make two devices compatible with each other baud rate is mentioned in the serial communication so that the transmission becomes easy and error free.

38. With what frequency UART operates( where f denoted the crystal frequency )?
a) f/12
b) f/32
c) f/144
d) f/384
Answer: d
Explanation: UART frequency is the crystal frequency f/12 divided by 32, that comes out to be f/384.

39. What is the function of the SCON register?
a) to control SBUF and SMOD registers
b) to program the start bit, stop bit, and data bits of framing
c) to control SMOD registers
d) none of the mentioned
Answer: b
Explanation: SCON register is mainly used for programming the start bits, stop bits and data bits of framing. As it consists of bits like RB8, TB8, SM0, SM1, SM2 etc.

40. What should be done if we want to double the baud rate?
a) change a bit of the TMOD register
b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
Answer: b
Explanation: PCON register consists of SMOD bit as its D7 bit, so if we set this bit then the baud rate gets doubled.

41. Because of virtual memory, the memory can be shared among ____________
a) processes
b) threads
c) instructions
d) none of the mentioned
Answer: a
Explanation: None.

42. _____ is the concept in which a process is copied into the main memory from the secondary memory according to the requirement.
a) Paging
b) Demand paging
c) Segmentation
d) Swapping
Answer: b
Explanation: None.

43. The pager concerns with the ____________
a) individual page of a process
b) entire process
c) entire thread
d) first page of a process
Answer: a
Explanation: None.

44. Swap space exists in ____________
a) primary memory
b) secondary memory
c) cpu
d) none of the mentioned
Answer: b
Explanation: None.

45. When a program tries to access a page that is mapped in address space but not loaded in physical memory, then ____________
a) segmentation fault occurs
b) fatal error occurs
c) page fault occurs
d) no error occurs
Answer: c
Explanation: None.

46. Effective access time is directly proportional to ____________
a) page-fault rate
b) hit ratio
c) memory access time
d) none of the mentioned
Answer: a
Explanation: None.

47. In FIFO page replacement algorithm, when a page must be replaced ____________
a) oldest page is chosen
b) newest page is chosen
c) random page is chosen
d) none of the mentioned
Answer: a
Explanation: None.

48. Which algorithm chooses the page that has not been used for the longest period of time whenever the page required to be replaced?
a) first in first out algorithm
b) additional reference bit algorithm
c) least recently used algorithm
d) counting based page replacement algorithm
Answer: c
Explanation: None.

49. A process is thrashing if ____________
a) it is spending more time paging than executing
b) it is spending less time paging than executing
c) page fault occurs
d) swapping can not take place
Answer: a
Explanation: None.

50. Working set model for page replacement is based on the assumption of ____________
a) modularity
b) locality
c) globalization
d) random access
Answer: b
Explanation: None.

1. When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory
Answer: c
Explanation: For addition purposes, the destination address must always be an accumulator. Example- ADD A,R0; ADD A, @R1; ADD A,@ DPTR

2. DAA command adds 6 to the nibble if:
a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
Answer: b
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.

3. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
Answer: c
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of the register or some immediate value. So A-R4 is being executed.

4. A valid division instruction always makes:
a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
Answer: c
Explanation: When we divide two numbers then AC and CY become zero.

5. In 8 bit signed number operations, OV flag is set to 1 if:
a) a carry is generated from D7 bit
b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
Answer: d
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to 1.

6. In unsigned number addition, the status of which bit is important?
a) OV
b) CY
c) AC
d) PSW
Answer: b
Explanation: If unsigned numbers operations are involved, then the status of CY flag is important and in signed number operation the status of OV flag is important.

7. Which instructions have no effect on the flags of PSW?
a) ANL
b) ORL
c) XRL
d) All of the mentioned
Answer: d
Explanation: These instructions are the arithmetic operations and the flags are affected by the data copy instructions, so all these instructions don’t affect the bits of the flag.

8. ANL instruction is used _______
a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
d) none of the mentioned
Answer: c
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to mask the status of the bits of the register.

9. CJNE instruction makes _______
a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
d) none of the mentioned
Answer: d
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not equal and it resets CY if the destination address is larger then the source address and sets CY if the destination address is smaller then the source address.

10. XRL, ORL, ANL commands have _______
a) accumulator as the destination address and any register, memory or any immediate data as the source address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the source address
d) any register as the destination address and any immediate data as the source address
Answer: a
Explanation: These commands have accumulator as the destination address and any register, memory or any immediate data as the source address.

11. Why two pins for ground are available in ADC0804?
a) for controlling the ADCON0 and ADCON1 register of the controller
b) for controlling the analog and the digital pins of the controller
c) for both parts of the chip respectively
d) for isolate analog and digital signal
Answer: d
Explanation: Two grounds are available in ADC0804 to isolate analog signal from digital signal. This isolation provides accuracy in digital output.

12. What is the function of the WR pin?
a) its active high input used to inform ADC0804 to the end of conversion
b) its active low input used to inform ADC0804 to the end of conversion
c) its active low input used to inform ADC0804 to the start of conversion
d) its active high input used to inform ADC0804 to the start of conversion
Answer: c
Explanation: WR is active low input used to inform the ADC0804 to start the conversion process.

13. State which of the following statements are false?
a) CLK IN pin used for External Clock Input or Internal Clock with external RC element
b) INTR pin tells about the end of the conversion
c) ADC0804 IC is an 8 bit parallel ADC in the family of the ADC0800 series
d) None of the mentioned
Answer: d
Explanation: CLK IN pin is used to tell about the conversion time, INTR pin tells about the end of the conversion and ADC0804 has a resolution of 8 bits only so all three statements are true.

14. While programming the ADC0808/0809 IC what steps are followed?
a) select the analog channel, start the conversion, monitor the conversion, display the digital results
b) select the analog channel, activate the ALE signal (L to H pulse), start the conversion, monitor the conversion, read the digital results
c) select the analog channel, activate the ALE signal (H to L pulse), start the conversion, monitor the conversion, read the digital results
d) select the channel, start the conversion, end the conversion
Answer: b
Explanation: While programming the ADC0808/0809 IC firstly we need to select the channel from the A, B, C pins. Then we need to activate the ALE signal, this is needed to latch the address. Then we start the conversion from the WR pin. After monitoring the INTR pin we get to know about the end of the conversion. Then we activate the OE enable to read out data out of the ADC chip.

15. In ADC0808/0809 IC which pin is used to select Step Size?
a) Vref
b) Vin
c) Vref/2 & Vin
d) None of the mentioned
Answer: a
Explanation: Step Size is calculated by formula Vref/(2n). As ADC0808/0809 8-bit ADC value of n=8. Therefore formula becomes Vref/(28) = Vref/256. If Vref = 5V then Step Size will be 5/256 i.e. 19.53mV.

16. What is the difference between ADC0804 and MAX1112?
a) ADC0804 has 8 bits and MAX1112 has 1 bit for data output
b) ADC0804 is used for adc and dac conversions whereas MAX1112 is used for serial data transmissions
c) ADC0804 has 32 bits and MAX1112 has 3 bit for data output
d) None of the mentioned
Answer: a
Explanation: ADC0804 is used for parallel ADC and MAX1112 is used for serial ADC.

17. Which of the following statements are true about DAC0808?
a) parallel digital data to analog data conversion
b) it has current as an output
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: DAC0804 is used for parallel data to analog data conversion.

18. 8 input DAC has ________
a) 8 discrete voltage levels
b) 64 discrete voltage levels
c) 124 discrete voltage levels
d) 256 discrete voltage levels
Answer: d
Explanation: For n input DAC has 2^n discrete voltage levels.

19. INTR, WR signal is an input/output signal pin?
a) both are output
b) both are input
c) one is input and the other is output
d) none of the mentioned
Answer: c
Explanation: INTR pin tells about the end of the conversion (output) and WR pin tells us to start the conversion (input).

20. What is the function of the SCLK pin in MAX1112?
a) It is used to bring data in
b) It is used to bring data out and send in the control byte, one at a time
c) It is used to get output clock
d) It is used to get serial output
Answer: b
Explanation: SCLK is used to bring data out and send in the control byte.

21. How many rows and columns are present in a 16*2 alphanumeric LCD?
a) rows=2, columns=32
b) rows=16, columns=2
c) rows=16, columns=16
d) rows=2, columns=16
Answer: d
Explanation: 16*2 alphanumeric LCD has 2 rows and 16 columns.

22. How many data lines are there in a 16*2 alphanumeric LCD?
a) 16
b) 8
c) 1
d) 0
Answer: b
Explanation: There are eight data lines from pin no 7 to pin no 14 in an LCD.

23. Which pin of the LCD is used for adjusting its contrast?
a) pin no 1
b) pin no 2
c) pin no 3
d) pin no 4
Answer: c
Explanation: Pin no 3 is used for controlling the contrast of the LCD.

24. For writing commands on an LCD, RS bit is
a) set
b) reset
c) set & reset
d) none of the mentioned
Answer: b
Explanation: For writing commands on an LCD, RS pin is reset.

25. Which command of an LCD is used to shift the entire display to the right?
a) 0x1C
b) 0x18
c) 0x05
d) 0x07
Answer: a
Explanation: 0x1C is used to shift the entire display to the right.

26. Which command is used to select the 2 lines and 5*7 matrix of an LCD?
a) 0x01
b) 0x06
c) 0x0e
d) 0x38
Answer: d
Explanation: 0x38 is used to select the 2 lines and 5*7 matrix of an LCD.

27. Which of the following step/s is/are correct for sending data to an LCD?
a) set the R/W bit
b) set the E bit
c) set the RS bit
d) all of the mentioned
Answer: d
Explanation: To send data to an LCD, RS pin should be set so that LCD will come to know that it will receive data which has to display on the screen. R/W pin should be reset as data has to be displayed (i.e. write to the LCD). High to low pulse must be applied to the E pin when data is supplied to data pins of the LCD.

28. Which of the following step/s is/are correct to perform reading operation from an LCD?
a) low to high pulse at E pin
b) R/W pin is set high
c) low to high pulse at E pin & R/W pin is set high
d) none of the mentioned
Answer: c
Explanation: For reading operations, R/W pin should be made high and added to it, a low to high pulse is also generated at the E pin.

29. Which instruction is used to select the first row first column of an LCD?
a) 0x08
b) 0x0c
c) 0x80
d) 0xc0
Answer: c
Explanation: 0x80 is used to select the first row first column of an LCD.

30. The RS pin is _________ for an LCD.
a) input
b) output
c) input & output
d) none of the mentioned
Answer: a
Explanation: The RS pin is an input pin for an LCD.

31. Which of the following steps detects the key in a 4*4 keyboard matrix about the key that is being pressed?
a) masking of bits
b) ensuring that initially, all keys are open
c) checking that whether the key is actually pressed or not
d) all of the mentioned
Answer: d
Explanation: For detecting that whether the key is actually pressed or not, firstly this must be ensured that initially all the keys are closed. Then we need to mask the bits individually to detect that which key is pressed. Then we need to check that is the key actually pressed or not, by checking that whether the key pressed for a time more than 20 micro seconds.

32. What is described by this command: CJNE A,#00001111b, ROW1
a) it masks the bit and then jumps to the label where ROW1 is written
b) it makes the value of the accumulator 0FH and then jumps at the address where ROW1 label is written
c) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the value becomes equal
d) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if the value is not equal
Answer: d
Explanation: This particular command CJNE A,#00001111b, ROW1 compares the value of the accumulator with OFH and jumps to ROW1 address if the value is not equal.

33. To detect that in which column, the key is placed?
a) we can mask the bits and then check it
b) we can rotate the bits and then check that particular bit which is set or reset(according to the particular condition)
c) none of the mentioned
d) all of the mentioned
Answer: d
Explanation: We can mask or we can even rotate the bits to check that particularly in which column is the key placed.

34. In reading the columns of a matrix, if no key is pressed we should get all in binary notation
a) 0
b) 1
c) F
d) 7
Answer: b
Explanation: If no key is pressed, then all the keys show 1 as they are all connected to power supply.

35. If we need to operate a key of a keyboard in an interrupt mode, then it will generate what kind of interrupt?
a) ES
b) EX0/EX1
c) T0/T1
d) RESET
Answer: b
Explanation: If a key is to operate in an interrupt mode then it will generate an external hardware interrupt.

36. To identify that which key is being pressed, we need to:
a) ground all the pins of the port at a time
b) ground pins of the port one at a time
c) connect all the pins of the port to the main supply at a time
d) none of the mentioned
Answer: b
Explanation: To detect that which key is being pressed, we need to ground the pins one by one.

37. Key press detection and Key identification are:
a) the same processes
b) two different works are done in Keyboard Interfacing
c) none of the mentioned
d) any of the mentioned
Answer: b
Explanation: They are two different works that are involved in Keyboard Interfacing. One is used for checking that which key is being actually pressed and the other is used to check that is the key actually pressed or not.

38. Which bits of opcode specify the type of registers to be used in the register addressing mode?
a. LSB
b. MSB
c. both a & b
d. none of the above
ANSWER: a. LSB

39. Which base-register is preferred for address calculation of a byte that is to be accessed from program memory by base-register plus register-indirect addressing mode?
a. DPTR
b. PSW
c. PCON
d. All of the above
ANSWER: a. DPTR

40. What does the symbol ‘#’ represent in the instruction MOV A, #55H ?
a. Direct datatype
b. Indirect datatype
c. Immediate datatype
d. Indexed datatype
ANSWER: c. Immediate datatype

41. Which of the following is not an addressing mode of 8051?
a) register instructions
b) register specific instructions
c) indexed addressing
d) none
Answer: d

42. The storage of addresses that can be directly accessed is
a) external data RAM
b) internal data ROM
c) internal data RAM and SFRS
d) external data ROM and SFRS
Answer: c
Clarification: Only internal data RAM and SFRS can be directly
addressed in direct addressing mode.

43. The address register for storing the 16-bit addresses can only be
a) stack pointer
b) data pointer
c) instruction register
d) accumulator
Answer: b
Clarification: The address register for storing the 16-bit addresses
can only be data pointer.

44. The address register for storing the 8-bit addresses can be
a) R0 of the selected bank of register
b) R1 of the selected bank of register
c) Stack pointer
d) All of the mentioned
Answer: d
Clarification: The registers R0 and R1 of the selected bank of
registers or stack pointer can be used as address registers for
storing the 8-bit addresses.

45. The instruction, ADD A, R7 is an example of
a) register instructions
b) register specific instructions
c) indexed addressing
d) none
Answer: a
Clarification: In register instructions addressing mode, operands
are stored in the registers R0-R7 of the selected register bank. One
of these registers is specified in the instruction.

46. The addressing mode, in which the instructions has no source
and destination operands is
a) register instructions
b) register specific instructions
c) direct addressing
d) indirect addressing
Answer: b
Clarification: In register specific instructions addressing mode, the
instructions don’t have source and destination operands. Some of
the instructions always operate only on a specific register.

47. The instruction, RLA performs
a) rotation of address register to left
b) rotation of accumulator to left
c) rotation of address register to right
d) rotation of accumulator to right
Answer: b
Clarification: The instruction, RLA rotates accumulator left.

48. The instruction, ADD A, #100 performs
a) 100(decimal) is added to contents of address register
b) 100(decimal) is subtracted from the accumulator
c) 100(decimal) is added to contents of an accumulator
d) none
Answer: c
Clarification: Immediate data 100(decimal) is added to the
contents of the accumulator.

49. In which of these addressing modes, a constant is specified in
the instruction, after the opcode byte?
a) register instructions
b) register specific instructions
c) direct addressing
d) immediate mode
Answer: d
Clarification: In immediate mode, an immediate data, i.e. a
constant is specified in the instruction, after the opcode byte.

50. The only memory which can be accessed using indexed
addressing mode is
a) RAM
b) ROM
c) Main memory
d) Program memory
Answer: d
Clarification: Only program memory can be accessed using the
indexed addressing mode.

51. The data address of look-up table is found by adding the
contents of
a) accumulator with that of program counter
b) accumulator with that of program counter or data pointer
c) data register with that of program counter or accumulator
d) data register with that of program counter or data pointer
Answer: b
Clarification: The look-up table data address is found out by
adding the contents of register accumulator with that of the
program counter or data pointer.

1.The ARM core uses ____ Architecture.
a) RISC
b) CISC
c) Both
D) none
Answer : a

2. ARM Processor specifically designed for to reduce ___
a) Size
b) Power Consumption
C) both
d) none.
Answer :c

3.ARM Processor core is a key component of ___ bit embedded system.
a)8
b) 16
c)32
d)64
Answer :c

4.RISC Philosophy implemented with ___ major deign goals.
a) 4
b)6
c)8
d)16
Answer :a

5.____ is the processing of instruction broken down to smaller unit.
a) Pipeline
b) ALU
c) MCU
d) All
Answer :a

6.Register contains ___
a) Address
b) data
c) both
d) none
Answer :c

7.___ Instruction used to transfer the data between register and memory.
a) Load
b)store
c) both
d) none
Answer : c

8.The design rule s allow a RISC to be __
a)simpler
b) complicated
c) both
d) none
Answer : a

9.ARM means ___
a) Advance Risc Machine
b) Advance Review machine
c) Advance Risc mechanism
d) All
Answer :d

10.RISC means ____
a)Reduced Instruction set computer
b) Reduced Instruct set computer
C) both
d) None
Answer :

11.CISC means _____
a) Complicated Instruction set computer
b) completed Instruction set computer
C) both
d) None
Answer :

12.___ is used to communicate between part of the device
a) Bus
b) ALU
c) Address
d) Peripherals
Answer :a

13.____ is used to connect peripherals.
a) PCI
b) ALU
c) MCU
d) All
Answer :a

14.ARM bus has __ Architecture level.
a) 2
b) 3
c) 4
d) 5
Answer :a

15._____ level covers electrical characteristics.
a) Physical
b) logical
c)temporal
d) all
Answer :a

16.____ level govern communication between the processor and peripheral.
a) Physical
b) logical
c)temporal
d) all
Answer :b

17.AMBA bus was introduced in the year of _____
a)1996
b)2000
c)1998
d) 1990
Answer :a

18.AMBA means____
a) Advance microcontroller bus architecture
b) advance Machine bus architecture
C) both
d)none
Answer :a

19.____ is placed between main memory and core .
a)cache
b) RAM
c)ROM
d) all
Answer :a

20.____ is used to sped up data transfer
a)cache
b) RAM
c)ROM
d) all
Answer :a

21.____ doesn’t require refreshing.
a)SRAM
b) DRAM
c) PROM
d) EPROM
Answer :

22.____ interrupt controller available in ARM Processor.
a)2
b)3
c)4
d)5
Answer :a

23.____ memory require refreshing.
a)SRAM
b) DRAM
c) PROM
d) EPROM
Answer :b

24.SRAM means____
a)Static RAM
b) Stable RAM
c) Standard RAM
d) none.
Answer :a

25. Application of ARM processor is____
a) automotive
b) consumable
c) mobile
d) all
Answer :d

26.In ARM processor data items are placed in ____ file.
a)Register
b) I/O
c) memory
d) all
Answer :a

27.ARM instruction typically have ___ source register.
a)2
b)3
c)4
d)5
Answer :a

28.ALU means____
a) Arithmetic logic unit
b) Adder logic unit
c) both
d) none
Answer :a

29.MAU means ________
a) Multiply Accumulate unit
b) Multiple adder unit
c) Multiple accumulate unit
d) none
Answer :a

30.General purpose registers holds the _____
a) Data
b) Address
c)both
d) none
Answer :c

31.___ Register is used as the stack pointer.
a) r13
b) r14
c) r15
d) r16
Answer :a

32.____ register is called the link register.
a) r13
b) r14
c) r15
d) r16
Answer :b

33.In ARM program register has __ types
a) 2
b) 3
c) 4
d) 5
Answer :a

34. Privileged mode allows ___ access .
a) read
b) write
c) both
d) none
Answer :c

35. Non Privileged mode allows ___ access .
a) read
b) write
c) both
d) none
Answer :a

36. In ARM consists of ______ processor mode.
a) 7
b) 5
c) 4
d) 6
Answer :a

37.How many bank registers are available in ARM?
a) 20
b) 25
c) 30
d) 40
Answer :a

38. The SPSR store the ___ mode of CPSR
a) Present
b) previous
c) both
d) none
Answer :b

39.____ are used to stop specific interrupt.
a) Interrupt mask
b) Interrupt request
c) both
d) none
Answer :a

40. CPSR has ___ interrupt mask bits.
a)2
b) 5
c) 6
d) 4
Answer :

41.___ interrupt levels available on theARM processor.
a) 2
b) 5
c) 6
d) 4
Answer :a

42.____ is the mechanism of RISC processor.
a) pipeline
b) task
c) sequence
d) none
Answer :a

43. _____ is the process of loading instructions
a) Fetch
b) decode
c) Execute
d) all
Answer :a

44.____ is used to identify the instruction to be executed.
a)Fetch
b) decode
c) Execute
d) all
Answer :b

45.MMU means ____
a) Memory management unit
b) memory mask unit
c) main memory unit
d) none
Answer :a

46.MPU means ____
a) Memory protection unit
b) memory processor unit
c) multiple process unit
d) none
Answer :a

47.____ are used to extent the instruction set.
a) Coprocessor
b) pipeline
c) multiprocessor
d) none
Answer :a

48.____ is used to organize memory.
a) MMU
b) MPU
c) MCU
d) none
Answer :a

49.____ vector is used by external hardware to interrupt the normal execution.
a) Interrupt
b) mask
c) Pipeline
d) none
Answer :a

50.ARM instruction commonly take ___ operands.
a) 2
b) 3
c) both
d) none
Answer :c

51.Data processing instructions manipulate data within ___
a) registers
b) memory
c) address
d) all
Answer :

52.___ instruction used to add and subtract of 32 bits.
a) Arithmetic
b) logical
c) compare
d) all
Answer :a

53.____ instruction perform bitwise operations.
a) Arithmetic
b) logical
c) compare
d) all
Answer :b

54.____ instruction are used to test a register.
a) Arithmetic
b)logical
c) compare
d) all.
Answer :c

55. ___ instruction changes the flow of execution.
a) Arithmetic
b)logical
c) compare
d) Branch.
Answer :d

56.___ instruction used to load word in register.
A) LDR
b) STR
c) STRB
d) LDRB
Answer :a

57. ___ instruction used to save a word or byte from a register.
A)LDR
b) STR
c) STRB
d) LDRB
Answer :b

58.___ instruction used to load a byte in to a register.
A) LDR
b) STR
c) STRB
d) LDRB
Answer :d

59. ___ instruction used to save a byte from a register.
A) LDR
b) STR
c) STRB
d) LDRB
Answer :c

60.___ instruction used to carry out stack operations
a) Load
b) store
c) both
d) none
Answer :c

61.___ operation remove the data from the stack.
a) POP
b) PUSH
c) both
d) none
Answer :a

62. ___ operation place the data on to stack.
a)POPb)
PUSH
c) both
d) none
Answer :b

63. SW1 is a ___interrupt instruction.
a) Software
b) hardware
c) both
d) none
Answer :a

64.___ instruction change the content of memory with the content of register.
a) SWAP
b) load
c) store
d) add
Answer :a

65.____ instruction transfer the content of CPSR into a register file.
a)MRS
b) CPSR
c) MSR
d) none
Answer :a

66.____ instruction transfer the content of register into a CPSR file.
a)MRS
b) CPSR
c) MSR
d) none
Answer :c

67. ___ is called the system control coprocessor
a) CP15
b) CP16
c) CP18
d) CP17
Answer :a

68.THUMP has ___ code density.
a)higher
b) lower
c) medium
d) none
Answer :a

69. THUMP instruction is related to ___ bit .
a) 32
b) 16
c) 8
d)64
Answer :a

71.___ is used for arithmetic shift left.
a) ASR
b)ASL
c) CMP
d) CMN
Answer :b

72. ____ is used for logical shift left.
a) LSL
b) ASL
c) CMP
d)LSR
Answer :a

73. ____ is used for logical shift left.
a) LSL
b) ASL
c) CMP
d)LSR
Answer :d

74.___ is used for compare two 32-bit integer.
a) LSL
b) ASL
c) CMP
d)CMN
Answer :c

75. ___ is used for comparenegative two 32-bit integer.
a) LSL
b) ASL
c) CMP
d) CMN
Answer :d

76. AD microcontroller 7128 has ______ bytes of Flash memory.
a)126k
b)256k
c) 512
d) 1M
Answer :a

77. AD microcontroller 7128 has ______ bytes of SRAM
a)8k
b)16k
c)24k
d) none
Answer :a

78. AD microcontroller 7128 has ______ ADC channel.
a)8
b)10
c) 12
d) 24
Answer :b

79. The ARM7 core Support___
a) RISC
b) CISC
c) Both
d) None
Answer :a

80. AD microcontroller 7128 has____ Pin GPIO Port
a)14
b)28
c) 32
d) 42
Answer :b

81.ADC consists of up to ____single-ended inputs.
a)10
b) 12
c)16
d) 20
Answer :a

82. The ARM7 core is a ____it Reduced Instruction Set Computer
a) 32
b) 16
c)8
d)64
Answer :a

83. ARM supports____types of exceptions.
a)5
b) 4
c) 3
d) 2
Answer :a

84. ARM7TDMI has a total of ____ registers.
a)37
b)24
c)8
d)16
Answer :a

85. ARM7TDMI has a total of ____ General Purpose registers .
a)31
b) 24
c)8
d)16
Answer :a

86.ARM7TDMI has a total of ____ status registers .
a)6
b)24
c)8
d)16
Answer :a

87. Thumb code usually uses more instructions for the _____ job.
a)Same
b)different
c) both
d) none
Answer :a

88. The 128kBytes of Flash/EE are organised as_____ banks
a) 2
b)24
c)8
d)16
Answer :a

89. The MMR space provides an______ between the CPU and all on-chip peripherals
a)Interface
b) logic
c) link
d) none
Answer :a

90. _____is provided to service general-purpose interrupt handling of internal and external
events.
a)IRQ
b) FIQ
c) SWI
d) None
Answer :a

91. ___is provided to service data transfer or communication channel with low latency.
a)IRQ
b) FIQ
c) SWI
d) None
Answer :b

92. The minimum latency for FIQ or IRQ interrupts is ___ cycle
a) 5
b) 10
c)15
d)20
Answer :c

93. ____Bytes of SRAM are available to the user, organized as 2k X 32 bits.
a) 8k
b) 8M
c) 8G
d) 8
Answer :a

94. The access time reading or writing a MMR depends on the___
a)AMBA
b)AMCA
)AMDA
d)AMEA
Answer :a

95. The ARM7TDMI is an ARM7 core with ____additional features.
a) 4
b) 10
c)15
d)20
Answer :a

96. The ARM7TDMI T support for the _____
A )Thump
b)Multiplies
c)debug
d) none
Answer :a

97. The ARM7TDMI D support for ____
A )Thump
b)Multiplies
c)debug
d) none
Answer :c

98. The ARM7TDMI M support for ____
A )Thump
b)Multiplies
c)debug
d) none
Answer :b

99. ADC consists of a _____bit successive-approximation converter
a)12
b) 5
c) 16
d)24
Answer :a